參數(shù)資料
型號: MT58L32L36F
廠商: Micron Technology, Inc.
英文描述: 32K x 36, 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態(tài)RAM)
中文描述: 32K的× 36,3.3V的I / O的流量通過SyncBurst的SRAM(1兆,3.3V的輸入/輸出,流通式同步脈沖靜態(tài)內存)
文件頁數(shù): 14/17頁
文件大小: 327K
代理商: MT58L32L36F
1Mb: 64K x 18, 32K x 32/36 3.3V I/O, Flow-Through SyncBurst SRAM
MT58L64L18F.p65 – Rev. 9/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
14
1Mb: 64K x 18, 32K x 32/36
3.3V I/O, FLOW-THROUGH SYNCBURST SRAM
READ TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST
READ
tOEQ
tOELZ
tKQHZ
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
A2
(NOTE 1)
BWE#, GW#,
ADV# suspends burst.
DONT CARE
UNDEFINED
Deselect Cycle
(Note 4)
NOTE:
1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
4. Outputs are disabled
t
KQHZ after deselect.
t
AS
t
ADSS
t
AAS
t
WS
t
CES
t
AH
t
ADSH
t
AAH
t
WH
t
CEH
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ TIMING PARAMETERS
-7.5
-8.5
-10
SYM
t
KC
f
KF
t
KH
t
KL
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
MIN
8.8
MAX
MIN
10.0
MAX
MIN
15
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
113
100
66
1.9
1.9
1.9
1.9
4.0
4.0
7.5
8.5
10.0
1.5
1.5
3.0
4.0
3.0
4.0
4.2
4.2
5.0
5.0
5.0
5.0
0
0
0
4.2
5.0
5.0
-7.5
-8.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
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PDF描述
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