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參數(shù)資料
| 型號： | MT55L256V36F |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| 中文描述： | 8MB的：256K × 36，流量通過ZBT SRAM的（8兆流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 380K |
| 代理商： | MT55L256V36F |
9
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
FBGA PIN DESCRIPTIONS
x18
6R
6P
x32/x36
6R
6P
2A, 9A, 2B,
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
2A, 9A, 2B,
3P,
3R,
4P,
4R, 3P,
3R,
4P,
4R,
8P, 8R, 9P, 9R,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
5B
4A
–
–
8P, 8R, 9P,
5B
5A
4A
4B
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa; BWb#
controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd#
controls DQd’s and DQPd. Parity is only available on the x18 and x36
versions.
Synchronous Clock Enable: This active LOW input permits CLK to
propogate throughout the device. When CKE# is HIGH, the device
ignores the CLK input and effectively internally extends the
previous CLK cycle. This input must meet the setup and hold times
around the rising edge of CLK.
Read/Write: This input determines the cycle type when ADV/LD# is
LOW and is the only means for determining READs and WRITEs.
READ cycles may not be converted into WRITEs (and vice versa)
other than by loading a new address. A LOW on this pin permits
BYTE WRITE operations to meet the setup and hold times around
the rising edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This
active LOW, asynchronous input enables the
data I/O output drivers.
7A
7A
CKE#
Input
7B
7B
R/W#
Input
6B
6B
CLK
Input
3A
3A
CE#
Input
6A
6A
CE2#
Input
11H
11H
ZZ
Input
3B
3B
CE2
Input
8B
8B
OE#(G#)
Input
(continued on next page)
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PDF描述 |
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| MT55L64L32F1 | 64K x 32,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
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| MT58L128L18FT-10 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L256V36FF-10ES | 制造商:Cypress Semiconductor 功能描述: |
| MT55L256V36P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb ZBT SRAM |
| MT55L256V36PF7.5 | 制造商:MICRO CHIP 功能描述: |
| MT55L256V36PT10 | 制造商:Micron Technology Inc 功能描述: |
| MT55L256V36PT-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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