參數(shù)資料
型號(hào)： MT55L256V32F
廠(chǎng)商： Micron Technology, Inc.
英文描述： 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
中文描述： 8MB的：256K × 32，流量通過(guò)ZBT SRAM的（8兆流通式同步靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 7/25頁(yè)
文件大?。?/td> 380K
代理商： MT55L256V32F
7
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
TQFP PIN DESCRIPTIONS (CONTINUED)
x18
88
x32/x36
88
SYMBOL
R/W#
TYPE
Input
DESCRIPTION
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted into
WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising
edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
Mode: This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
SRAM Data I/Os: Byte “a” is associated with DQa pins; Byte
“b” is associated with DQb pins; Byte “c” is associated
with DQc pins; Byte “d” is associated with DQd pins.
Input data must meet setup and hold times around the
rising edge CLK.
31
31
MODE
(LBO#)
Input
(a)
58, 59, 62, 63,
68, 69, 72-74
(b)
8, 9, 12, 13,
18, 19, 22-24
(a)
52, 53, 56-59,
62, 63
(b)
68, 69, 72-75,
78, 79
(c)
2, 3, 6-9,
12, 13
(d)
18, 19, 22-25,
28, 29
51
80
1
30
15, 16, 41, 65, 91
DQa
Input/
Output
DQb
DQc
DQd
n/a
NC/
DQPa
NC/
DQPb
NC/
DQPc
NC/
DQPd
V
DD
NC/
I/O
No Connect/Data Bits: On the x32 version, these pins are
no connect (NC) and can be left floating or connected to
GND to minimize thermal impedance. On the x36 version,
these bits are DQs.
Power Supply:
See DC Electrical Characteristics and
Operating Conditions for range.
Isolated Output Buffer Supply:
See DC Electrical
Characteristics and Operating Conditions for range.
Ground:
GND.
15, 16, 41, 65, 91
Supply
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 17, 21,
26, 40, 55, 60,
66, 67, 71, 76, 90
1-3, 6, 7, 25,
28-30, 51-53, 56,
57, 75, 78, 79,
95, 96
38, 39, 42, 43
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 17, 21,
26, 40, 55, 60,
66, 67, 71, 76, 90
n/a
V
DD
Q
Supply
V
SS
Supply
NC
–
No Connect: These pins can be left floating or connected
to GND to minimize thermal impedance.
38, 39, 42, 43
DNU
–
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
No Function: This pin is internally connected to the die and
will have the capacitance of an input pin. It is allowable to
leave this pin unconnected or driven by signals. Pin 84 is
reserved as an address pin for the 16Mb ZBT SRAM.
84
84
NF
–
相關(guān)PDF資料
PDF描述
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