參數(shù)資料
型號: MT55L256V32F
廠商: Micron Technology, Inc.
英文描述: 8Mb: 256K x 32,F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器)
中文描述: 8MB的:256K × 32,流量通過ZBT SRAM的(8兆流通式同步靜態(tài)存儲器)
文件頁數(shù): 21/25頁
文件大?。?/td> 380K
代理商: MT55L256V32F
21
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
READ/WRITE TIMING
WRITE
D(A1)
1
2
3
4
5
6
7
8
9
CLK
tKHKH
tKLKH
tKHKL
10
CE#
tKHCX
tCVKH
R/W#
CKE#
tKHEX
tEVKH
BWx#
ADV/LD#
tKHAX
tAVKH
ADDRESS
A1
A2
A3
A4
A5
A6
A7
tKHDX
tDVKH
DQ
COMMAND
tKHQX1
D(A1)
D(A2)
Q(A4)
Q(A3)
D(A2+1)
tKHQX
tKHQZ
tKHQV
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
OE#
tGLQV
tGLQX
tGHQZ
DON’T CARE
UNDEFINED
D(A5)
tKHQX
Q(A4+1)
D(A7)
Q(A6)
NOTE:
1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
-10
-11
-12
SYM
t
GHQZ
t
AVKH
t
EVKH
t
CVKH
t
DVKH
t
KHAX
t
KHEX
t
KHCX
t
KHDX
MIN
MAX
5.0
MIN
MAX
5.0
MIN
MAX
5.0
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
2.2
2.2
2.2
2.2
0.5
0.5
0.5
0.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
READ/WRITE TIMING PARAMETERS
-10
-11
-12
SYM
t
KHKH
f
KF
t
KHKL
t
KLKH
t
KHQV
t
KHQX
t
KHQX1
t
KHQZ
t
GLQV
t
GLQX
MIN
10
MAX
MIN
11
MAX
MIN
12
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
100
90
83
2.5
2.5
3.0
3.0
3.0
3.0
7.5
8.5
9.0
3.0
3.0
3.0
3.0
3.0
3.0
5.0
5.0
5.0
5.0
5.0
5.0
0
0
0
相關(guān)PDF資料
PDF描述
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