參數(shù)資料
型號(hào)： MT55L256V18P1
廠商： Micron Technology, Inc.
英文描述： 2.5V I/O，256K x 18,Flow-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器)
中文描述： 2.5VI /輸出，256 × 18，流量通過(guò)ZBT SRAM的電壓（2.5V輸入/輸出，4Mb的流通式同步靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 6/25頁(yè)
文件大?。?/td> 434K
代理商： MT55L256V18P1
6
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS
x18
37
36
x32/x36
37
36
32-35, 44-50,
81, 82, 99, 100
SYMBOL TYPE
SA0
SA1
SA
DESCRIPTION
Input
Synchronous Address Inputs: These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. Pins 83 and 84 are reserved as address bits
for higher-density 8Mb and 16Mb ZBT SRAMs, respectively.
SA0 and SA1 are the two least significant bits (LSB) of the
address field and set the internal burst counter if burst is
desired.
Synchronous Byte Write Enables: These active LOW inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK.
BYTE WRITEs need to be asserted on
the same cycle as the address.
BWs are associated with
addresses and apply to subsequent data. BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls DQc
pins; BWd# controls DQd pins.
Clock: This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising
edge. All synchronous inputs must meet setup and hold
times around the clock
’
s rising edge.
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input can
be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input can
be used for memory depth expansion.
Output Enable: This
active LOW, asynchronous input
enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Clock Enable: This active LOW input permits
CLK to propagate throughout the device. When CKE# is
HIGH, the device ignores the CLK input and effectively
internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ is
active, all other inputs are ignored.
32-35, 44-50,
80-82, 99, 100
93
94
–
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
97
97
CE2
Input
86
86
OE#
(G#)
Input
85
85
ADV/LD# Input
87
87
CKE#
Input
64
64
ZZ
Input
(continued on next page)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT55L256V18P1T 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Micron Technology Inc 功能描述:
MT55L256V18P1T-10 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:
MT55L256V18P1T-6 制造商:Micron Technology Inc 功能描述:256K X 18 ZBT SRAM, 3.5 ns, PQFP100
MT55L256V18P1T-7.5TR 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Micron Technology Inc 功能描述:
MT55L256V32P 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:8Mb ZBT SRAM
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