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| 型號(hào)： | MT55L256V18P1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2.5V I/O，256K x 18,Flow-Through ZBT SRAM(2.5V輸入/輸出,4Mb流通式同步靜態(tài)存儲(chǔ)器) |
| 中文描述： | 2.5VI /輸出，256 × 18，流量通過(guò)ZBT SRAM的電壓（2.5V輸入/輸出，4Mb的流通式同步靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 18/25頁(yè) |
| 文件大小： | 434K |
| 代理商： | MT55L256V18P1 |
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18
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_2.p65
–
Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
PRELIMINARY
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
NOTE:
1. This parameter is sampled.
2. Measured as HIGH above V
IH
and LOW below V
IL
.
3. Refer to Technical Note TN-55-01,
“
Designing with ZBT SRAMs,
”
for a more thorough discussion on these parameters.
4. This parameter is sampled.
5. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
6. Transition is measured ±200mV from steady state voltage.
7. OE# can be considered a
“
Don
’
t Care
”
during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
9. Test conditions as specified with output loading shown in Figure 1 for 3.3V I/O (V
DD
Q = +3.3V ±0.165V) and Figure 3
for 2.5V I/O (V
DD
Q = +2.5V +0.4V/-0.125V).
10. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9) (0
°
C
≤
T
A
≤
+70
°
C; V
DD
= +3.3V ±0.165V; ZBT mode)
-6
-7.5
-10
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
t
KHKH
f
KF
t
KHKL
t
KLKH
6.0
7.5
10
ns
166
133
100
MHz
ns
ns
1.7
1.7
2.0
2.0
3.2
3.2
1
1
t
KHQV
t
KHQX
t
KHQX1
t
KHQZ
t
GLQV
t
GLQX
t
GHQZ
3.5
4.2
5.0
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2
2, 3, 4, 5
2, 3, 4, 5
6
2, 3, 4, 5
2, 3, 4, 5
3.5
3.5
3.5
4.2
3.5
5.0
0
0
0
3.5
4.2
5.0
t
AVKH
t
EVKH
t
CVKH
t
DVKH
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
ns
ns
ns
ns
7
7
7
7
t
KHAX
t
KHEX
t
KHCX
t
KHDX
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
7
7
7
7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L256V18P1T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Micron Technology Inc 功能描述: |
| MT55L256V18P1T-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT55L256V18P1T-6 | 制造商:Micron Technology Inc 功能描述:256K X 18 ZBT SRAM, 3.5 ns, PQFP100 |
| MT55L256V18P1T-7.5TR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Micron Technology Inc 功能描述: |
| MT55L256V32P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb ZBT SRAM |
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