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參數(shù)資料
| 型號： | MT4C4M4E9DJS |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 MEG x 4 EDO DRAM |
| 中文描述： | 4邁可× 4 EDO公司的DRAM |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 360K |
| 代理商： | MT4C4M4E9DJS |
17
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
DON’T CARE
UNDEFINED
tCLZ
tOFF
OPEN
VALID DATA
OPEN
COLUMN
ROW
tCAC
tRAC
tAA
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCRP
tRCD
tRSH
tRAS
tRP
tCHR
tRAS
DQxV
VIOL
V
IL
ADDR
V
IL
V
IL
RAS#
tOE
tOD
CASL#/CASH#
V
IL
OE#
tORD
HIDDEN REFRESH CYCLE
1
(WE# = HIGH; OE# = LOW)
-5
-6
SYMBOL
t
OE
t
OFF
t
ORD
t
RAC
t
RAD
t
RAH
t
RAS
t
RCD
t
RP
t
RSH
MIN
MAX
12
12
MIN
MAX
15
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
50
60
9
9
50
11
30
13
12
10
60
14
40
15
10,000
10,000
TIMING PARAMETERS
-5
-6
SYMBOL
t
AA
t
AR
t
ASC
t
ASR
t
CAC
t
CAH
t
CHR
t
CLZ
t
CRP
t
OD
MIN
MAX
25
MIN
MAX
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
38
0
0
45
0
0
13
15
8
8
0
5
0
10
10
0
5
0
12
15
NOTE:
1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
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