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參數(shù)資料
| 型號： | MT4C1004J |
| 廠商： | Austin Semiconductor, Inc |
| 英文描述： | 4 MEG x 1 DRAM FAST PAGE MODE |
| 中文描述： | 4邁可× 1 DRAM的快速頁面模式 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 130K |
| 代理商： | MT4C1004J |
2-29
MT4C1004J 883C
REV. 11/97
DS000021
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT5C1005 883C
256K x 4 SRAM
4 MEG x 1 DRAM
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled, not 100% tested.
Capacitance is measured with Vcc = 5V, f = 1 MHz at
less than 50mVrms, T
= 25
°
C
±
3
°
C, Vbias = 2.4V
applied to each input and output individually with
remaining inputs and outputs open.
3. I
CC
is dependent on cycle rates.
4. I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (-55
°
C
≤
T
≤
125
°
C) is assured.
7. An initial pause of 100
μ
s is required after power-up
followed by eight
/
R
A
/
S refresh cycles (
/
R
/
A
/
S-ONLY or
CBR with
/
W
/
E HIGH) before proper device operation
is assured. The eight
/
R
/
A
/
S cycle wake-up should be
repeated any time the 16ms refresh requirement is
exceeded.
8. AC characteristics assume
t
T = 5ns.
9. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
10. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
11. If
/
C
/
A
/
S = V
IH
, data output is High-Z.
12. If
/
C
/
A
/
S = V
IL
, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to 2 TTL gates and
100pF.
14. Assumes that
t
RCD <
t
RCD (MAX). If
t
RCD is greater
than the maximum recommended value shown in this
table,
t
RAC will increase by the amount that
t
RCD
exceeds the value shown.
15. Assumes that
t
RCD
≥
t
RCD (MAX).
16. If
/
C
/
A
/
S is LOW at the falling edge of
/
R
/
A
/
S, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer,
/
C
/
A
/
S must be
pulsed HIGH for
t
CPN.
17. Operation within the
t
RCD (MAX) limit ensures that
t
RAC (MAX) can be met.
t
RCD (MAX) is specified as
a reference point only; if
t
RCD is greater than the
specified
t
RCD (MAX) limit, then access time is
controlled exclusively by
t
CAC.
18. Operation within the
t
RAD (MAX) limit ensures that
t
RCD (MAX) can be met.
t
RAD (MAX) is specified as
a reference point only; if
t
RAD is greater than the
specified
t
RAD (MAX) limit, then access time is
controlled exclusively by
t
AA.
19. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
20.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
21.
t
WCS,
t
RWD,
t
AWD and
t
CWD are restrictive
operating parameters in LATE WRITE, READ-WRITE
and READ-MODIFY-WRITE cycles only. If
t
WCS
≥
t
WCS (MIN), the cycle is an EARLY-WRITE cycle and
the data output will remain an open circuit through-
out the entire cycle. If
t
RWD
≥
t
RWD (MIN),
t
AWD
≥
t
AWD (MIN) and
t
CWD
≥
t
CWD (MIN), the cycle is a
READ-WRITE and the data output will contain data
read from the selected cell. If neither of the above
conditions are met, the cycle is a LATE-WRITE and
the state of Q is indeterminate (at access time and
until
/
C
/
A
/
S goes back to V
IH
).
22. These parameters are referenced to
/
C
/
A
/
S leading edge
in EARLY-WRITE cycles and
W
/
E leading edge in
LATE-WRITE or READ-WRITE cycles.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case
W
/
E = LOW.
24.
t
WTS and
t
WTH are set up and hold specifications for
the
W
/
E pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of
t
WRP and
t
WRH in the
CBR REFRESH cycle.
25. JEDEC test mode only.
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