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參數(shù)資料
| 型號(hào)： | MT4C1004J |
| 廠商： | Austin Semiconductor, Inc |
| 英文描述： | 4 MEG x 1 DRAM FAST PAGE MODE |
| 中文描述： | 4邁可× 1 DRAM的快速頁面模式 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 130K |
| 代理商： | MT4C1004J |
2-24
MT4C1004J 883C
REV. 11/97
DS000021
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT5C1005 883C
256K x 4 SRAM
4 MEG x 1 DRAM
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C
boundary. The FAST PAGE MODE cycle is always initi-
ated with a row address strobed-in by
/
R
/
A
/
S followed by a
column address strobed-in by
/
C
/
A
/
S.
/
C
/
A
/
S may be toggled-in
by holding
/
R
/
A
/
S
LOW and strobing-in different column
addresses, thus executing faster memory cycles. Returning
/
R
/
A
/
S HIGH terminates the FAST PAGE MODE operation.
Returning
/
R
//
A
/
S and
/
C
/
A
/
S HIGH terminates a memory cycle
and decreases chip current to a reduced standby level. Also,
the chip is preconditioned for the next cycle during the
/
R
/
A
/
S HIGH time. Memory cell data is retained in its correct state
by maintaining power and executing any
/
R
A
/
S cycle (READ,
WRITE,
/
R
A
/
S-ONLY,
/
C
/
A
/
S-BEFORE-
/
R
/
A
/
S, or HIDDEN
RE-
FRESH) so that all 1,024 combinations
of
/
R
A
/
S
addresses
(A0-A9) are executed at least every 16ms, regardless of
sequence. The
/
C
A
/
S- BEFORE-
/
R
A
/
S cycle will
invoke the
refresh counter for automatic
/
R
/
A
/
S addressing.
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS
10
11
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
MEMORY
ARRAY
SENSE AMPLIFIERS
I/O GATING
Vcc
Vss
10
D
REFRESH
COUNTER
WE
CAS
DATA OUT
BUFFER
DATA IN
BUFFER
11
Q
*EARLY-WRITE
DETECTION CIRCUIT
4096
1024
1
*NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)
4096
COLUMN
DECODER
R
D
11
COLUMN
ADDRESS
BUFFER(11)
ROW
ADDRESS
BUFFERS (11)
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PDF描述 |
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| MT4C1004J883C | 4 MEG x 1 DRAM FAST PAGE MODE |
| MT4S03AU | SILICON NPN EPITAXIAL PLANAR TYPE |
| MT4S06 | TOSHIBA TRANSISTOR SILICON NPN EPITAXIAL PLANAR TYPE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4C1004J883C | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:4 MEG x 1 DRAM FAST PAGE MODE |
| MT4C1004JCN-100/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/IT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/XT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-120/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
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