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參數(shù)資料
| 型號： | MT4C1004J |
| 廠商： | Austin Semiconductor, Inc |
| 英文描述： | 4 MEG x 1 DRAM FAST PAGE MODE |
| 中文描述： | 4邁可× 1 DRAM的快速頁面模式 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 130K |
| 代理商： | MT4C1004J |
2-34
MT4C1004J 883C
REV. 11/97
DS000021
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT5C1005 883C
256K x 4 SRAM
4 MEG x 1 DRAM
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C
4 MEG POWER-UP AND REFRESH
CONSTRAINTS
The EIA/ JEDEC 4 Meg DRAM introduces two potential
incompatibilities compared to the previous generation
1 Meg DRAM. The incompatibilities involve refresh and
power-up. Understanding these incompatibilities and pro-
viding for them will offer the designer and system user
greater compatibility between the 1 Meg and 4 Meg.
REFRESH
The most commonly used refresh mode of the 1 Meg is
the CBR (
C
A
/
S-BEFORE-
R
A
/
S) REFRESH cycle. The CBR for
the 1 Meg specifies the
W
/
E pin as a “don’t care.” The 4 Meg,
on the other hand, specifies the CBR REFRESH mode with
the
W
/
E pin held at a voltage HIGH level.
A CBR cycle with
W
/
E LOW will put the 4 Meg into the
JEDEC specified test mode (WCBR).
POWER-UP
The 4 Meg JEDEC test mode constraint may introduce
another problem. The 1 Meg POWER-UP cycle requires a
100
μ
s delay followed by any eight
R
A
/
S cycles. The 4 Meg
POWER-UP is more restrictive in that eight
R
A
/
S-ONLY or
CBR REFRESH (
W
/
E held HIGH) cycles must be used. The
restriction is needed since the 4 Meg may power-up in the
JEDEC specified test mode and must exit out of the test
mode. The only way to exit the 4 Meg JEDEC test mode is
with either a
R
A
/
S-ONLY or a CBR REFRESH cycle (
W
/
E
held HIGH).
SUMMARY
1. The 1 Meg CBR REFRESH allows the
W
/
E pin to be
“don’t care” while the 4 Meg CBR requires
W
/
E to be
HIGH.
2. The eight
R
A
/
S wake-up cycles on the 1 Meg may be any
valid
R
A
/
S cycle while the 4 Meg may only use
R
A
/
S-
ONLY or CBR REFRESH cycles (
W
/
E held HIGH).
COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR
DON’T CARE
tRP
V
IL
RAS
tRAS
OPEN
tCHR
tCSR
V
IL
CAS
V
OL
Q
tRP
tRAS
tRPC
tCSR
tRPC
tCHR
tCPN
V
IL
V
IL
tWRP
tWRH
CBR REFRESH: WE
tWRP
tWRH
V
IL
WCBR TEST MODE: WE
tWTS
tWTH
tWTS
tWTH
DRAM
DRAM
CBR REFRESH: WE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT4C1004J883C | 4 MEG x 1 DRAM FAST PAGE MODE |
| MT4S03AU | SILICON NPN EPITAXIAL PLANAR TYPE |
| MT4S06 | TOSHIBA TRANSISTOR SILICON NPN EPITAXIAL PLANAR TYPE |
| MT4S100T | UHF LOW NOISE AMPLIFIER APPLICATION |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4C1004J883C | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:4 MEG x 1 DRAM FAST PAGE MODE |
| MT4C1004JCN-100/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/IT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/XT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-120/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
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