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參數(shù)資料
| 型號： | MT4C1004J |
| 廠商： | Austin Semiconductor, Inc |
| 英文描述： | 4 MEG x 1 DRAM FAST PAGE MODE |
| 中文描述： | 4邁可× 1 DRAM的快速頁面模式 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 130K |
| 代理商： | MT4C1004J |
2-23
MT4C1004J 883C
REV. 11/97
DS000021
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
MT5C1005 883C
256K x 4 SRAM
4 MEG x 1 DRAM
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C
4 MEG x 1 DRAM
FAST PAGE MODE
AV AILABLE AS MILITARY
SPECIFICATONS
SMD 5962-90622
MIL-STD-883
FEATURES
Industry standard x1 pinout, timing, functions and
packages
High-performance, CMOS silicon-gate process
Single +5V
±
10% power supply
Low-power, 2.5mW standby; 300mW active, typical
All inputs, outputs and clocks are fully TTL and CMOS
compatible
1,024-cycle refresh distributed across 16ms
Refresh modes:
/
R
A
/
S-ONLY,
/
C
/
A
/
S-BEFORE-
/
R
/
A
/
S
(CBR),
and HIDDEN
FAST PAGE MODE access cycle
CBR with
W
/
E a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS
Timing
70ns access
80ns access
100ns access
120ns access
MARKING
- 7
- 8
-10
-12
Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic SOJ
Ceramic ZIP
Ceramic Gull Wing
CN
C
ECN
ECJ
CZ
ECG
No. 101
No. 102
No. 202
No. 504
No. 400
No. 600
PIN ASSIGNMENT (Top View)
GENERAL DESCRIPTION
The MT4C1004J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x1 configu-
ration. During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits which are entered 11
bits (A0-A10) at a time.
/
R
/
A
/
S is used to latch the first 11 bits
and
/
C
/
A
/
S the latter 11 bits. A READ or WRITE cycle is
selected with the
W
/
E input. A logic HIGH on
W
/
E dictates
READ mode while a logic LOW on
W
/
E dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of
W
/
E or
/
C
/
A
/
S, whichever occurs last. If
W
/
E
goes LOW prior to
/
C
/
A
/
S going LOW, the output pin remains
open (High-Z) until the next
/
C
/
A
/
S cycle. If
W
/
E goes LOW
after data reaches the output pin, Q is activated and retains
the selected cell data as long as
/
C
/
A
/
S remains LOW (regard-
less of
W
/
E or
/
R
/
A
/
S). This LATE-
W
/
E pulse results in a
READ-WRITE cycle. FAST PAGE MODE operations allow
faster data operations (READ, WRITE or READ-MODIFY-
WRITE) within a row-address (A0-A10) defined page
*Address not used for
/
R
/
A
//
S-ONLY REFRESH
18-Pin DIP
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
D
WE
RAS
*A10
A0
A1
A2
A3
Vcc
Vss
Q
CAS
A9
A8
A7
A6
A5
A4
A9
Q
D
RAS
NC
A0
A2
Vcc
A5
A7
CAS
Vss
WE
A10*
NC
A1
A3
A4
A6
A8
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
20-Pin ZIP
D
WE
RAS
NC
*A10
A0
A1
A2
A3
Vcc
Vss
Q
CAS
NC
A9
A8
A7
A6
A5
A4
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
1
20-Pin SOJ
20-Pin LCC
20-Pin Gull Wing
DRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT4C1004J883C | 4 MEG x 1 DRAM FAST PAGE MODE |
| MT4S03AU | SILICON NPN EPITAXIAL PLANAR TYPE |
| MT4S06 | TOSHIBA TRANSISTOR SILICON NPN EPITAXIAL PLANAR TYPE |
| MT4S100T | UHF LOW NOISE AMPLIFIER APPLICATION |
| MT4S34U | SILICON NPN EPITAXIAL PLANAR TYPE VHF-UHF BAND LOW NOISE AMPLIFIER APLICATIONS. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4C1004J883C | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:4 MEG x 1 DRAM FAST PAGE MODE |
| MT4C1004JCN-100/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/IT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-100/XT | 制造商:Micross Components 功能描述:DRAM, 4MB - Rail/Tube |
| MT4C1004JCN-120/883C | 制造商:Micross Components, Inc. 功能描述:DRAM, 4MB - Rail/Tube |
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