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| 型號(hào)： | MT47H128M8HV-187ELIT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, FBGA-60 |
| 文件頁(yè)數(shù)： | 90/133頁(yè) |
| 文件大小： | 9170K |
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List of Tables
Table 1: Key Timing Parameters ...................................................................................................................... 2
Table 2: Addressing ......................................................................................................................................... 2
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions .......................................................................... 17
Table 4: Input Capacitance ............................................................................................................................ 22
Table 5: Absolute Maximum DC Ratings ........................................................................................................ 23
Table 6: Temperature Limits .......................................................................................................................... 24
Table 7: Thermal Impedance ......................................................................................................................... 25
Table 8: General IDD Parameters .................................................................................................................... 26
Table 9: IDD7 Timing Patterns (8-Bank Interleave READ Operation) ................................................................. 27
Table 10: DDR2 IDD Specifications and Conditions (Die Revisions E, G, and H) ................................................ 28
Table 11: AC Operating Specifications and Conditions .................................................................................... 31
Table 12: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 42
Table 13: ODT DC Electrical Characteristics ................................................................................................... 43
Table 14: Input DC Logic Levels ..................................................................................................................... 44
Table 15: Input AC Logic Levels ..................................................................................................................... 44
Table 16: Differential Input Logic Levels ........................................................................................................ 45
Table 17: Differential AC Output Parameters .................................................................................................. 47
Table 18: Output DC Current Drive ................................................................................................................ 47
Table 19: Output Characteristics .................................................................................................................... 48
Table 20: Full Strength Pull-Down Current (mA) ............................................................................................ 49
Table 21: Full Strength Pull-Up Current (mA) ................................................................................................. 50
Table 22: Reduced Strength Pull-Down Current (mA) ..................................................................................... 51
Table 23: Reduced Strength Pull-Up Current (mA) .......................................................................................... 52
Table 24: Input Clamp Characteristics ........................................................................................................... 53
Table 25: Address and Control Balls ............................................................................................................... 54
Table 26: Clock, Data, Strobe, and Mask Balls ................................................................................................. 54
Table 27: AC Input Test Conditions ................................................................................................................ 55
Table 28: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) ................................................... 57
Table 29: DDR2-667/800/1066 Setup and Hold Time Derating Values (tIS and tIH) .......................................... 58
Table 30: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe ..................................................... 61
Table 31: DDR2-667/800/1066 tDS, tDH Derating Values with Differential Strobe ............................................ 62
Table 32: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb .................................................. 63
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 ..................................... 63
Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 ..................................... 64
Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 ..................................... 64
Table 36: Truth Table – DDR2 Commands ..................................................................................................... 69
Table 37: Truth Table – Current State Bank n – Command to Bank n ............................................................... 70
Table 38: Truth Table – Current State Bank n – Command to Bank m .............................................................. 72
Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 73
Table 40: Burst Definition .............................................................................................................................. 77
Table 41: READ Using Concurrent Auto Precharge ......................................................................................... 98
Table 42: WRITE Using Concurrent Auto Precharge ....................................................................................... 104
Table 43: Truth Table – CKE ......................................................................................................................... 119
1Gb: x4, x8, x16 DDR2 SDRAM
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MT47H128M8HV-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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