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參數(shù)資料
| 型號： | MT47H128M8HV-187ELIT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, FBGA-60 |
| 文件頁數(shù)： | 132/133頁 |
| 文件大?。?/td> | 9170K |
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READ with Auto Precharge
If A10 is high when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock
edge that is AL + (BL/2) cycles later than the read with auto precharge command provi-
ded tRAS (MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at this rising clock
edge, the start point of the auto precharge operation will be delayed until tRAS (MIN) is
satisfied. If tRTP (MIN) is not satisfied at this rising clock edge, the start point of the
auto precharge operation will be delayed until tRTP (MIN) is satisfied. When the inter-
nal precharge is pushed out by tRTP, tRP starts at the point where the internal pre-
charge happens (not at the next rising clock edge after this event).
When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE
command is AL + (tRTP + tRP)/tCK. When BL = 8, the minimum time from READ with
auto precharge to the next ACTIVATE command is AL + 2 clocks + (tRTP + tRP)/tCK. The
term (tRTP + tRP)/tCK is always rounded up to the next integer. A general purpose equa-
tion can also be used: AL + BL/2 - 2CK + (tRTP + tRP)/tCK. In any event, the internal
precharge does not start earlier than two clocks after the last 4-bit prefetch.
READ with auto precharge command may be applied to one bank while another bank is
operational. This is referred to as concurrent auto precharge operation, as noted in Ta-
ble 41. Examples of READ with precharge and READ with auto precharge with applica-
ble timing requirements are shown in Figure 52 (page 99) and Figure 53 (page 100),
respectively.
Table 41: READ Using Concurrent Auto Precharge
From Command (Bank n)
To Command (Bank m)
Minimum Delay
(with Concurrent Auto Precharge)
Units
READ with auto precharge
READ or READ with auto precharge
BL/2
tCK
WRITE or WRITE with auto precharge
(BL/2) + 2
tCK
PRECHARGE or ACTIVATE
1
tCK
1Gb: x4, x8, x16 DDR2 SDRAM
READ
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
98
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HV-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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