參數(shù)資料
型號： MT47H128M8HV-187ELIT:E
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝： 8 X 11.50 MM, FBGA-60
文件頁數(shù)： 131/133頁
文件大小： 9170K
not be issued until tRP is met. However, part of the row precharge time is hidden during
the access of the last data elements.
Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 50 and in Figure 51
for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is AL + BL/
2 - 2CK + MAX (tRTP/tCK or 2 × CK) where MAX means the larger of the two.
Figure 50: READ-to-PRECHARGE – BL = 4
CK
CK#
T0
T1
T2
Don’t Care
Transitioning Data
T3
T4
T5
T6
T7
Address
Bank a
≥t
RAS (MIN)
≥t
RTP (MIN)
≥t
RP (MIN)
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
Command
READ
NOP
PRE
ACT
NOP
4-bit
prefetch
DQ
DO
A10
Valid
CL = 3
AL = 1
DQS, DQS#
≥t
RC (MIN)
Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 4.
2. tRTP
≥ 2 clocks.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 51: READ-to-PRECHARGE – BL = 8
CK
CK#
T0
T1
T2
Don’t Care
Transitioning Data
T3
T4
T5
T6
T7
T8
CL = 3
AL = 1
DQS, DQS#
First 4-bit
prefetch
Second 4-bit
prefetch
≥
tRTP (MIN)
≥
tRP (MIN)
Address
Bank a
≥
tRC (MIN)
≥
tRAS (MIN)
A10
Valid
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
DQ
DO
Command
READ
NOP
ACT
PRE
Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 8.
2. tRTP
≥ 2 clocks.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
1Gb: x4, x8, x16 DDR2 SDRAM
READ
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
97
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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