參數(shù)資料
型號: MT47H128M8HV-187ELIT:E
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝: 8 X 11.50 MM, FBGA-60
文件頁數(shù): 129/133頁
文件大小: 9170K
Figure 47: Nonconsecutive READ Bursts
Command
READ
NOP
READ
T0
T1
T2
T3
T3n
T4
T5
T7
T8
T6
T4n
T6n
T7n
CK
CK#
T5
T7
T8
T5n
T6
T4n
T7n
Command
NOP
READ
NOP
READ
T0
T1
T2
T3
T4
DQ
DO
n
DO
b
Don’t Care
Transitioning Data
Address
Bank,
Col n
Bank,
Col b
Address
Bank,
Col n
Bank,
Col b
CK
CK#
CL = 4
CL = 3
DQ
DO
n
DO
b
DQS, DQS#
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Three subsequent elements of data-out appear in the programmed order following
DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecu-
tive READs.
1Gb: x4, x8, x16 DDR2 SDRAM
READ
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
95
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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