- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224506 > MT46V32M81AZ4-6T:G 32M X 4 DDR DRAM, 0.75 ns, PDSO66 PDF資料下載
參數(shù)資料
| 型號： | MT46V32M81AZ4-6T:G |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP-66 |
| 文件頁數(shù)： | 39/82頁 |
| 文件大小： | 2866K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁
128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
44
2000 Micron Technology, Inc. All rights reserved.
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSNR has been met (if the
previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the com-
mands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given com-
mand is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no regis-
ter accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been termi-
nated.
Write:A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been ter-
minated
Read with Auto Precharge Enabled: See following text – 3a
Write with Auto Precharge Enabled: See following text – 3a
3a.
The read with auto precharge enabled or write with auto precharge enabled states can each be bro-
ken into two parts: the access period and the precharge period. For read with auto precharge, the
precharge period is defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still accesses all of the data in
the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR
measured as if auto precharge was disabled. The access period starts with registration of the com-
mand and ends where the precharge period (or tRP) begins.
Table 10:
Truth Table – Current State Bank n - Command to Bank m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
CS#
RAS#
CAS#
WE#
COMMAND/ACTION
NOTES
Any
HX
X
DESELECT (NOP/continue previous operation)
LH
H
NO OPERATION (NOP/continue previous operation)
Idle
XX
X
Any Command Otherwise Allowed to Bank m
Row
Activating,
Active, or
Precharging
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7
LL
H
L
PRECHARGE
Read
(Auto-
Precharge
Disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7
LH
L
WRITE (select column and start WRITE burst)
7, 9
LL
H
L
PRECHARGE
Write
(Auto-
Precharge
Disabled)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 8
LH
L
WRITE (select column and start new WRITE burst)
7
LL
H
L
PRECHARGE
Read
(With Auto-
Precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start new READ burst)
7, 3a
LH
L
WRITE (select column and start WRITE burst)
7, 9, 3a
LL
H
L
PRECHARGE
Write
(With Auto-
Precharge)
LL
H
ACTIVE (select and activate row)
LH
L
H
READ (select column and start READ burst)
7, 3a
LH
L
WRITE (select column and start new WRITE burst)
7, 3a
LL
H
L
PRECHARGE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT47H128M8HV-187ELIT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| MT48LC32M4A2P-7ELIT:G | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| MT55L256L18FT-12TR | 256K X 18 ZBT SRAM, 9 ns, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V32M82ZZ5-75 ES | 制造商:Micron Technology Inc 功能描述:32MX8 SDRAM DDR PLASTIC PBF FBGA 2.5V - Trays |
| MT46V32M82ZZ5-75EZ | 制造商:Micron Technology Inc 功能描述:32MX8 DDR SDRAM PLASTIC 2.5V - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。