參數(shù)資料
型號(hào)： MT46V32M81AZ4-6T:G
元件分類： DRAM
英文描述： 32M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 22/82頁(yè)
文件大?。?/td> 2866K
128Mb: x4, x8, x16
DDR SDRAM
09005aef8074a655
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MBDDRx4x8x16_2.fm - Rev. J 7/04 EN
29
2000 Micron Technology, Inc. All rights reserved.
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 20.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst and after the
tWR time.
NOTE:
For the WRITE commands used in the follow-
ing illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered on the first rising edge of DQS follow-
ing the WRITE command, and subsequent data ele-
ments will be registered on successive edges of DQS.
The LOW state on DQS between the WRITE command
and the first rising edge is known as the write pream-
ble; the LOW state on DQS following the last data-in
element is known as the write postamble.
The time between the WRITE command and the
first corresponding rising edge of DQS (tDQSS) is
specified with a relatively wide range (from 75 per-
cent to 125 percent of one clock cycle and 72
percent to 128 percent of one clock cycle for
DDR400). All of the WRITE diagrams show the nom-
inal case, and where the two extreme cases (i.e.,
tDQSS [MIN] and tDQSS [MAX]) might not be intui-
tive, they have also been included. Figure 21 on
page 30 shows the nominal case and the extremes of
tDQSS for a burst of 4. Upon completion of a burst,
assuming no other commands have been initiated,
the DQ will remain High-Z and any additional input
data will be ignored.
Data for any WRITE burst may be concatenated
with or truncated with a subsequent WRITE com-
mand. In either case, a continuous flow of input data
can be maintained. The new WRITE command can be
issued on any positive edge of clock following the pre-
vious WRITE command. The first data element from
the new burst is applied after either the last element of
a completed burst or the last desired data element of a
longer burst which is being truncated. The new WRITE
command should be issued x cycles after the first
WRITE command, where x equals the number of
desired data element pairs (pairs are required by the
2n-prefetch architecture).
Figure 22 on page 31 shows concatenated bursts of
4. An example of nonconsecutive WRITEs is shown in
Figure 23 on page 32. Full-speed random write
accesses within a page or pages can be performed as
Figure 20: WRITE Command
Data for any WRITE burst may be followed by a sub-
sequent READ command. To follow a WRITE without
truncating the WRITE burst, tWTR should be met as
Data for any WRITE burst may be truncated by a
subsequent READ command, as shown in Figure 26 on
Note that only the data-in pairs that are registered
prior to the tWTR period are written to the internal
array, and any subsequent data-in should be masked
with DM as shown in Figure 27 on page 36.
Data for any WRITE burst may be followed by a sub-
sequent PRECHARGE command. To follow a WRITE
without truncating the WRITE burst, tWR should be
met as shown in Figure 28 on page 37.
Data for any WRITE burst may be truncated by a
subsequent PRECHARGE command, as shown in
that only the data-in pairs that are registered prior to
the tWR period are written to the internal array, and
any subsequent data-in should be masked with DM as
shown in Figures 29 and 30. After the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met.
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BA0,1
HIGH
EN AP
DIS AP
BA
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
x4: A0–A9, A11
x8: A0–A9
x16: A0–A8
x8: A11
x16: A9, A11
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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