參數(shù)資料
型號： MSC8144EC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, PLASTIC, FCBGA-783
文件頁數(shù)： 76/80頁
文件大小： 1239K
代理商： MSC8144EC
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 10
Revision History
Freescale Semiconductor
78
9
Aug 2008
Removed the comment about preliminary estimates before Table 4 and removed non-DDR rows in the
table.
Table 9 and Table 11 for DDR and DDR2 SDRAM capacitance removed and subsequent tables
renumbered.
Changed units for IOH and IOL to mA in Table 9.
Removed signal low and high input current from Table 12.
Added a note to Table 15 to exclude TDM and TMS. Removed reference to overshoot and undershoot and
associated figure.
Changed TRST deassertion description in Section 3.1.
Changed minimum clock frequency to 33 MHz and maximum clock frequency to 133 MHz in Table 16.
Deleted old Table 17 Clock Parameters.
Changed minimum input clock frequency to 33 MHz in Table 19.
Changed the tDDKHAX minimum value in Table 23 to 1.85 ns.
Removed tREFPJ and tREFCJ from Table 24 because the specifications are not required or tested.
Removed tPCRSTCLK, tPCRSTOFF, tPCRST, and tPCRHFA from Table 36 because the specifications are not
required or tested.
Removed tUAVKH and tUAVXH from Table 38 because the specifications are not required or tested.
The parameters tMDCH, tMDCR, and tMDHF were removed from Table 40 because the specifications are not
required or tested.
The parameters tMTXH/tMTX, tMTXR, and tMTXF were removed from Table 41 because the specifications
are not required or tested.
The parameters tMRXH/tMRX, tMRXR, and tMRXF were removed from Table 42 because the specifications
are not required or tested.
The parameters tRMXH/tRMX, tRMXR, and tRMXF, were removed from Table 43 because the specifications
are not required or tested.
Removed the parameters tRGT, tRGTH/tRGT (1000Base-T), tRGTH/tRGT (10Base-T), tRGTR, tRGTF, tG12, and
tG125H/tG125 were removed from Table 45 and Table 46 because the specifications are not required or
tested.
Changed tUEKHOX to guaranteed by design in Table 47.
Updated Figure 35 and Figure 36 SPI timing diagrams.
Removed TCK rise and fall time from Table 50.
10
Aug 2008
Changed b8t to bit in the M3 memory description on the first page.
Changed maximum input high voltage (VIH) for SPI to 3.465 in the first row of Table 14.
Changed packet processor to QUICC Engine Subsystem in the last row of Table 18.
Table 66. Document Revision History (continued)
Revision
Date
Description
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MSC8144ESVT1000B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA BOX - Trays 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
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MSC8144ESVT800B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ETVT1000A 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk
MSC8144ETVT1000B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
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