參數(shù)資料
型號(hào)： MSC8144EC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, PLASTIC, FCBGA-783
文件頁數(shù)： 29/80頁
文件大小： 1239K
代理商： MSC8144EC
Electrical Characteristics
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 10
Freescale Semiconductor
35
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
2.6.1
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.2
describes the clocking characteristics. Section 2.6.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144EC device:
PORESET and TRST must be asserted externally for the duration of the power-up sequence using the VDDIO (3.3 V)
supply. See Table 19 for timing. TRST must be deasserted before normal operation begins to ensure correct
initialization of the Security Engine.
Note:
For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
VDDM3IO (2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.
CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation
(see Figure 6). 32 cycles should be accounted only after VDDIO reaches its nominal value.
CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after
power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows
during power-up.
Figure 6 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply.
2.6.2
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 16 shows the maximum frequency values for
CLKIN and PCI_CLK_IN. The user must ensure that maximum frequency values are not exceeded.
Figure 6. Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO
Table 16. Clock Frequencies
Characteristic
Symbol
Min
Max
Unit
CLKIN frequency
FCLKIN
33
133
MHz
PCI_CLK_IN frequency
FPCI_CLK_IN
33
133
MHz
CLKIN duty cycle
DCLKIN
40
60
%
PCI_CLK_IN duty cycle
DPCI_CLK_IN
40
60
%
Vo
lt
a
g
e
Time
3.3 V
VDDIO Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET
1
VDDIO applied
1.0 V
VDDIO = Nominal
VDD = Nominal
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