參數(shù)資料
型號： MSC8144EC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, PLASTIC, FCBGA-783
文件頁數(shù)： 42/80頁
文件大?。?/td> 1239K
代理商： MSC8144EC
Electrical Characteristics
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 10
Freescale Semiconductor
47
2.6.5.5
Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance
shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to 0.8
× baud frequency. This includes contributions from internal circuitry, the package, and any external components related to the
receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is
100
Ω resistive for differential return loss and 25 Ω resistive for common mode.
Table 32. Receiver AC Timing Specifications—1.25 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mVPP
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UIPP
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
UIPP
Measured at receiver
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 13. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
800
ps
±100 ppm
Table 33. Receiver AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mVPP
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UIPP
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
UIPP
Measured at receiver
Total Jitter Tolerance
JT
0.65
UIPP
Measured at receiver. Total jitter is composed of
three components, deterministic jitter, random jitter
and single frequency sinusoidal jitter. The sinusoidal
jitter may have any amplitude and frequency in the
unshaded region of Figure 13. The sinusoidal jitter
component is included to ensure margin for low
frequency jitter, wander, noise, crosstalk and other
variable system effects.
Multiple Input Skew
SMI
24
ns
Skew at the receiver input between lanes of a
multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
400
ps
±100 ppm
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