參數(shù)資料
型號(hào)： MSC8101VT1500F
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 64/104頁(yè)
文件大小： 0K
描述： IC DSP 16BIT 250MHZ 332-FCPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： SC140 內(nèi)核
接口： 通信處理器模塊（CPM）
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 512kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.60V
工作溫度： -40°C ~ 75°C
安裝類型： 表面貼裝
封裝/外殼： 332-BFBGA，F(xiàn)CPBGA
供應(yīng)商設(shè)備封裝： 332-FCBGA（17x17）
包裝： 托盤
MSC8101 Technical Data, Rev. 19
2-22
Freescale Semiconductor
Physical and Electrical Specifications
Figure 2-17 shows Host DMA write timing.
2.6.7
CPM Timings
Figure 2-17.
Host DMA Write Timing Diagram, HPCR[OAD] = 0
Table 2-20.
CPM Input Characteristics
No.
Characteristic
Typical
Unit
39
FCC input set-up time before low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
10
5
ns
17
FCC input hold time after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
0
3
ns
18
SCC/SMC/SPI/I2C input set-up time before low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
20
5
ns
19
SCC/SMC/SPI/I2C input hold time after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial clock input)
0
5
ns
20
TDM input set-up time before low-to-high serial clock transition
5
ns
21
TDM input hold time after low-to-high serial transition
5
ns
22
PIO/TIMER/DMA input set-up time before low-to-high serial clock transition
10
ns
23
PIO/TIMER/DMA input hold time after low-to-high serial clock transition
3
ns
Note:
FCC, SCC, SMC, SPI, I2C are Non-Multiplexed Serial Interface signals.
Table 2-21.
CPM Output Characteristics
No.
Characteristic
Min
Max
Unit
41
FCC output delay after low-to-high clock transition
a. internal clock (BRGxO)
b. external clock (serial input clock)
0
2
6
18
ns
TX[0–3]
Write
Data
Valid
63
64
46
45
47
48
(Output)
HREQ
HACK
HD[0–15]
(Output)
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