參數(shù)資料
型號: MSC8101VT1500F
廠商: Freescale Semiconductor
文件頁數(shù): 58/104頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 250MHZ 332-FCPBGA
標準包裝: 90
系列: StarCore
類型: SC140 內(nèi)核
接口: 通信處理器模塊(CPM)
時鐘速率: 300MHz
非易失內(nèi)存: 外部
芯片上RAM: 512kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.60V
工作溫度: -40°C ~ 75°C
安裝類型: 表面貼裝
封裝/外殼: 332-BFBGA,F(xiàn)CPBGA
供應商設備封裝: 332-FCBGA(17x17)
包裝: 托盤
AC Timings
MSC8101 Technical Data, Rev. 19
Freescale Semiconductor
2-17
2.6.5.2 DMA Data Transfers
Table 2-18 describes the DMA signal timing.
The DREQ
signal is synchronized with the falling edge of DLLIN. DONE timing is relative to the rising edge of DLLIN.
To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-18.
Figure 2-11 shows synchronous peripheral interaction.
Table 2-18.
DMA Signals
Number
Characteristic
Minimum
Maximum
Units
72
DREQ set-up time before DLLIN falling edge
6
ns
73
DREQ hold time after DLLIN falling edge
0.5
ns
74
DONE set-up time before DLLIN rising edge
9
ns
75
DONE hold time after DLLIN rising edge
0.5
ns
76
DACK/DRACK/DONE delay after DLLIN rising edge
0.5
9
ns
Figure 2-11.
DMA Signals
DLLIN
DREQ
DONE Input
DACK/DONE/DRACK Outputs
73
72
74
75
76
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