參數(shù)資料
型號(hào): MSC7118VM1200
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 53/60頁(yè)
文件大?。?/td> 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: StarCore
類型: 定點(diǎn)
接口: 主機(jī)接口,I²C,UART
時(shí)鐘速率: 300MHz
非易失內(nèi)存: ROM(8 kB)
芯片上RAM: 464kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA
供應(yīng)商設(shè)備封裝: 400-MAPBGA(17x17)
包裝: 托盤
Revision History
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Freescale Semiconductor
57
7
Revision History
Table 32 provides a revision history for this data sheet.
Table 32. Document Revision History
Revision
Date
Description
0
Sep. 2005
Initial public release.
1
Oct 2005
Added explanatory note to HDI16 timing table.
2
Oct. 2005
Added information about signals GPIOB11, GPIOC11, GPIOD7, and GPIOD8 to the signal descriptions
and pinout location lists.
3
Dec. 2005
Added information about signals GPIOA16, GPIOA17, GPIOA27, GPIOA28, and GPIOA29 to signal
description and pinout location lists.
4
Nov. 2006
Updated Reference Manual reference to MSC711x Reference Manual.
Updated arrows in Host DMA Writing Timing figure.
5
Jul. 2007
Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.
Added a note to clarify the definition of TCK timing 700 in new Table 31.
Removed references to VCCSYN and VCCSYN1 in the new power supply design recommendation Section
3.2.
6
Aug 2007
The power-up and power-down sequences described in Section 3.2 starting on page 42 have been expanded
to five possible design scenarios/cases. These cases replace the previously recommended
power-up/power-down sequence recommendations. Section 3.2 has been clarified by adding subsection
headings.
7
Apr 2008
Change the PLL filter resistor from 20
Ω to 2 Ω in Section 3.2.5.
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