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| 型號： | MSC7118VM1200 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSP 16BIT W/DDR CTRLR 400-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | StarCore |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，I²C，UART |
| 時(shí)鐘速率： | 300MHz |
| 非易失內(nèi)存： | ROM（8 kB） |
| 芯片上RAM： | 464kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.20V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 400-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 400-MAPBGA（17x17） |
| 包裝： | 托盤 |
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MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Hardware Design Considerations
Freescale Semiconductor
40
3.2
This section outlines the MSC7118 power considerations: power supply, power sequencing, power planes, decoupling, power
supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power
consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.
3.2.1
Power Supply
The MSC7118 requires four input voltages, as shown in Table 28.
You should supply the MSC7118 core voltage via a variable switching supply or regulator to allow for compatibility with
possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across VDDC
and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and reference voltages supply
the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM and GND. The reference voltage
is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 × VDDM. Refer to the JEDEC standard JESD8
(Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements.
3.2.2
Power Sequencing
One consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied.
The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is
extremely important to observe the power up and power down sequences at the board level to avoid latch-up, forward biasing
of ESD devices, and excessive currents, which all lead to severe device damage.
Note:
There are five possible power-up/power-down sequence cases. The first four cases listed in the following sections are
recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated
for current spike risks based on actual information for the specific application.
Table 28. MSC7118 Voltages
Voltage
Symbol
Value
Core
VDDC
1.2 V
Memory
VDDM
2.5 V
Reference
VREF
1.25 V
I/O
VDDIO
3.3 V
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相關(guān)代理商/技術(shù)參數(shù) |
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| MSC7119 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7119_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC |
| MSC7119VF1200 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC FASTSTAR DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MSC7119VM1200 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC FASTSTAR DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MSC711XADS | 功能描述:開發(fā)板和工具包 - 其他處理器 DEV SYS FOR FSL 711X DEV RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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