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參數(shù)資料
| 型號(hào)： | MSC1202Y3RHHT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQCC36 |
| 封裝： | GREEN, PLASTIC, QFN-36 |
| 文件頁(yè)數(shù)： | 49/93頁(yè) |
| 文件大?。?/td> | 1093K |
| 代理商： | MSC1202Y3RHHT |
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MSC1200
MSC1201
MSC1202
SBAS317E APRIL 2004 REVISED MAY 2006
www.ti.com
53
Serial Data Buffer 0 (SBUF0)
7
6
5
4
3
2
1
0
Reset Value
SFR 99h
00h
SBUF0
Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive
bits 70
buffers are separate registers, but both are addressed at this location.
SPI Control (SPICON)
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ah
SBIT3
SBIT2
SBIT1
SBIT0
ORDER
CPHA
ESS
CPOL
00h
SBIT30
Serial Bit Count. Number of bits transferred (read-only).
bits 74
SBIT3:0
COUNT
0x00
0
0x01
1
0x03
2
0x02
3
0x06
4
0x07
5
0x05
6
0x04
7
0x0C
8
ORDER
Set Bit Order for Transmit and Receive.
bit 3
0: Most significant bits first
1: Least significant bBits first
CPHA
Serial Clock Phase Control.
bit 2
0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
ESS
Enable Slave Select.
bit 1
0: SS (P1.4) is configured as a general-purpose I/O (default).
1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is
high-impedance when SS is high.
CPOL
Serial Clock Polarity.
bit 0
0: SCK idle at logic low
1: SCK idle at logic high
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| MSC1202Y3RHHTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Precision ADC & DAC w/8051 CPU & Flash RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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