
NXP Semiconductors
MPT612
Maximum power point tracking IC
MPT612
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NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2010
7 of 7
Symbol
Pin
33
[3]
Type Description
PVVOLTSENSEBOOST
I
PV Voltage sense for boost mode; this pin is not connected when only buck
mode is used
PVCURRENTSENSE
34
[3]
38
[3]
I
PV Current sense.
PIO25/AD6
I/O
PIO25:
general purpose digital input and output pin.
I
AD6:
analog-to-digital converter input 6
PIO26/AD7
39
[3]
I/O
PIO26:
general purpose digital input and output pin
I
AD7:
analog-to-digital
input 7
PIO27/ TRST
8
[1]
I/O
PIO27:
general purpose digital input and output pin
I
TRST : Test Reset for the JTAG interface
[6]
PIO28/TMS
9
[1]
I/O
PIO28:
general purpose digital input and output pin.
TMS:
Test Mode Select for the JTAG interface
[6]
I
PIO29/TCK
10
[1]
I/O
PIO29:
General purpose input/output digital pin.
TCK:
Test Clock for the JTAG interface
[6]
This clock must be slower than
1
/
6
of the CPU clock (CCLK) for the JTAG
interface to operate
I
PIO30/TDI/MAT3_3
15
[1]
I/O
PIO30:
general purpose digital input and output pin
TDI:
Test Data In for JTAG interface
[6]
I
O
MAT3_3:
PWM output 3 for timer 3
PIO31/TDO
16
[1]
O
PIO31:
general purpose digital output pin
TDO:
Test Data Out for JTAG interface
[6]
O
RTCX1
20
[8][9]
25
[8][9]
26
[8]
I
RTC oscillator circuit input; the input voltage must not exceed 1.8 V
RTCX2
O
RTC oscillator circuit output
RTCK
I/O
Returned test clock output; bidirectional pin with internal pull-up; extra signal
added to the JTAG port. Assists debugger synchronization when processor
frequency varies
XTAL1
11
I
oscillator and internal clock generator circuit input; the input voltage must
not exceed 1.8 V
XTAL2
JTAGSEL
12
27
O
I
oscillator amplifier output
JTAG interface select; input with internal pull-down:
when LOW, the device operates normally
when externally pulled HIGH at reset, PIO27 to PIO31 are configured as
JTAG port and the part is in Debug mode
RST
6
I
external reset input; TTL with hysteresis; 5 V tolerant
when LOW, this pin resets the device; all I/O ports and peripherals return
to their default states and processor execution will begin at address 0x00
GND
7,19,4
3
I
ground; 0 V reference
GNDADC
31
I
analog ground 0 V reference; nominally the same voltage as GND but
should be isolated to minimize noise and error
V
DD(ADC)
42
I
analog 3.3 V power supply; nominally the same voltage as V
DD(IO)
but should
be isolated to minimize noise and error; the level on this pin provides the
ADC voltage reference level
V
DDC
5
I
1.8 V core power supply; internal circuitry and on-chip PLL power supply
voltage