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參數(shù)資料
| 型號： | MPT612FBD48 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Maximum power point tracking IC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48 |
| 文件頁數(shù)： | 22/37頁 |
| 文件大?。?/td> | 607K |
| 代理商： | MPT612FBD48 |
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NXP Semiconductors
MPT612
Maximum power point tracking IC
MPT612
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2010
22 of 22
Symbol
Oscillator pins
Parameter
Conditions
Min
Typ
Max
Unit
V
i(XTAL1)
input voltage on pin
XTAL1
0
-
1.8
V
V
o(XTAL2)
output voltage on pin
XTAL2
0
-
1.8
V
V
i(RTCX1)
input voltage on pin
RTCX1
0
-
1.8
V
V
o(RTCX2)
output voltage on pin
RTCX2
0
-
1.8
V
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25
°
C), nominal supply voltages.
[2] Core and internal rail.
[3] External rail.
[4] If V
DD(IO)
< 3.0 V, the I/O pins are not 5 V tolerant and the ADC input voltage is limited to V
DD(ADC)
= 3.0 V.
[5] If V
DD(ADC)
< 3.0 V, the I/O pins are not 5 V tolerant.
[6] The RTC typically fails when V
DD(RTC)
drops below 1.6 V.
[7] Including voltage on outputs in 3-state mode.
[8] V
DD(IO)
supply voltages must be present.
[9] 3-state outputs go into 3-state mode when V
DD(IO)
is grounded.
[10] Accounts for 100 mV voltage drop in all supply lines.
[11] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[12] Minimum condition for V
I
= 4.5 V, maximum condition for V
I
= 5.5 V. V
DD(ADC)
≥
3.0 V and V
DD(IO)
≥
3.0 V.
[13] Applies to PIO25:16.
[14] Battery supply current on pin V
DD(RTC)
.
[15] Input leakage current to GND.
Table 5.
V
DD(ADC)
= 2.5 V to 3.6 V; T
amb
= -40
°
C to +85
°
C unless otherwise specified. ADC frequency 4.5 MHz
Symbol
Parameter
V
IA
analog input voltage
C
ia
analog input capacitance
E
D
differential linearity error
E
L(adj)
integral non-linearity
E
O
offset error
E
G
gain error
E
T
absolute error
ADC Static Characteristics
Conditions
Min
0
Typ
-
Max
V
DD(ADC)
1
Unit
V
-
-
pF
[1][2][3]
-
-
±1
LSB
[1][2][4]
-
-
±2
LSB
[1][5]
-
-
±3
LSB
[1][6]
-
-
±0.5
%
[1][7]
-
-
±4
LSB
[1] Conditions: GNDADC
= 0 V, V
DD(ADC)
= 3.3 V and V
DD(IO)
= 3.3 V for 10-bit resolution at full speed; V
DD(ADC)
= 2.6 V, V
DD(IO)
= 2.6 V for
8-bit resolution at full speed.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See
Fig 4.
[4] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See
Fig 4.
[5] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See
Fig 4.
[6] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error and the straight line which fits the ideal transfer curve. See
Fig 4.
[7] The absolute error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See
Fig 4.
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