參數(shù)資料
型號(hào): MPT612FBD48
廠商: NXP SEMICONDUCTORS
元件分類: 模擬信號(hào)調(diào)理
英文描述: Maximum power point tracking IC
中文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48
文件頁數(shù): 10/37頁
文件大?。?/td> 607K
代理商: MPT612FBD48
NXP Semiconductors
MPT612
Maximum power point tracking IC
7.4 Memory map
The MPT612 memory map incorporates several distinct regions, as shown in
Fig 3
. In
addition, the CPU interrupt vectors can be re-mapped to allow them to reside in either
flash memory (the default) or on-chip static RAM.
001aam090
AHB PERIPHERALS
0xFFFF FFFF
0xF000 0000
0xE000 0000
4.0 GB
3.75 GB
3.5 GB
0xC000 0000
0x4000 0000
0x8000 0000
0x7FFF E000
0x7FFF DFFF
0x4000 2000
0x4000 1FFF
0x0000 8000
0x0000 7FFF
0x0000 0000
0.0 GB
1.0 GB
2.0 GB
3.0 GB
APB PERIPHERALS
RESERVED ADDRESS SPACE
BOOT BLOCK
RESERVED ADDRESS SPACE
RESERVED ADDRESS SPACE
8 kB ON-CHIP STATIC RAM
32 kB ON-CHIP NON-VOLATILE MEMORY
Fig 3.
System Memory Map
7.5 Interrupt controller
The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored
IRQ and non-vectored IRQ as defined by programmable settings. The programmable
assignment scheme means that priorities of interrupts from the various peripherals can
be dynamically assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ because the
FIQ service routine does not need to branch into the interrupt service routine but can run
MPT612
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2010
10 of 10
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