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參數(shù)資料
| 型號： | mPD705101GM-100-8ED |
| 廠商： | NEC Corp. |
| 英文描述： | V831TM 32-BIT MICROPROCESSOR |
| 中文描述： | V831TM 32位微處理器 |
| 文件頁數(shù)： | 39/72頁 |
| 文件大?。?/td> | 302K |
| 代理商： | MPD705101GM-100-8ED |
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μ
PD705101
39
Instruction
Operand(s)
Format
CY
OV
S
Z
Function
MULI
imm16,
reg1, reg2
V
–
–
–
–
Saturatable multiplication of signed 32-bit
operands. reg1 and imm16, sign-extended to
32 bits, are multiplied together as signed
integers.
[If no overflow has occurred:]
The result is written into reg2.
[If an overflow has occurred:]
The SAT bit is set. If the result is positive,
the positive maximum is written into reg2; if
the result is negative, the negative maximum
is written into reg2.
MULT3
reg1, reg2,
reg3
VIII
–
–
–
–
Saturatable multiplication of signed 32-bit
operands. reg1 and reg2 are multiplied
together as signed integers. The high-order
32 bits of the product are written into reg3.
MULU
reg1, reg2
I
–
Multiplication of unsigned operands. reg1 and
reg2 are multiplied together as unsigned values.
The high-order 32 bits of the product (double
word) are written into r30 and the low-order
32 bits are written into reg2.
NOP
III
–
–
–
–
No operation.
NOT
reg1, reg2
I
–
0
NOT. The NOT (ones complement) of reg1 is
taken and written into reg2.
OR
reg1, reg2
I
–
0
OR. The OR of reg2 and reg1 is taken and
written into reg2.
ORI
imm16,
reg1, reg2
V
–
0
OR. The OR of reg1 and imm16, zero-
extended to a word, is taken and written into
reg2.
OUT.B
reg2,
disp16[reg1]
VI
–
–
–
–
Port output. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
port address. The low-order one byte of the
data in reg2 is output to the resulting port
address.
OUT.H
reg2,
disp16[reg1]
VI
–
–
–
–
Port output. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
port address. The low-order two bytes of the
data in reg2 are output to the resulting port
address. Bit 0 of the unsigned 32-bit port
address is masked to 0.
OUT.W
reg2,
disp16[reg1]
VI
–
–
–
–
Port output. disp16, sign-extended to a word,
is added to reg1 to produce an unsigned 32-bit
port address. The word of data in reg2 is output
to the produced port address. Bits 0 and 1 of the
unsigned 32-bit port address are masked to 0.
RETI
IX
Return from trap/interrupt handling routine.
The return PC and PSW are read from the
system registers so that program execution will
return from the trap or interrupt handling routine.
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