參數(shù)資料
型號： mPD705101GM-100-8ED
廠商： NEC Corp.
英文描述： V831TM 32-BIT MICROPROCESSOR
中文描述： V831TM 32位微處理器
文件頁數(shù)： 18/72頁
文件大?。?/td> 302K
代理商： MPD705101GM-100-8ED
μ
PD705101
18
9. SERIAL INTERFACE FUNCTION
The following channels are provided for the serial interface function.
Asynchronous serial interface (UART) : 1 channel
Clocked serial interface (CSI)
Baud rate generator (BRG)
: 1 channel
: 1 channel
9.1 Asynchronous Serial Interface (UART)
The features of the asynchronous serial interface (UART) are as follows:
Full duplex communication. Receive buffer (RXB) is provided (transmit buffer (TXB) is not provided).
Two-pin configuration (The UART of the V831 does not have the SCLK and CTS pins.)
TXD: Transmit data output pin
RXD: Receive data input pin
Transfer rate: 150 bps to 76800 bps (bus clock: 33 MHz, with BRG)
Baud rate generator
Serial clock source can be selected from band rate generator output or bus clock (
φ
)
Receive error detection function
Parity error
Framing error
Overrun error
Three interrupt sources
Receive error interrupt (INTSER)
The interrupt is generated by ORing three types of receive errors.
Receive end interrupt (INTSR)
The receive end interrupt request is generated after completion of receive data transfer from the shift register
to the receive buffer in the reception enabled status.
Transmit end interrupt (INTST)
The transmit end interrupt is generated after completion of serial transfer of transmit data (9, 8, or 7 bits) from
the shift register. The character length of the transmit/receive data is specified by the ASIM00 and ASIM01
registers.
Character length : 7 or 8 bits
: 9 bits (with extension bit appended)
Parity function
Transmit stop bit: 1 or 2 bits
: Odd, even, 0, or none
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