參數(shù)資料
型號： mPD705101GM-100-8ED
廠商： NEC Corp.
英文描述： V831TM 32-BIT MICROPROCESSOR
中文描述： V831TM 32位微處理器
文件頁數(shù)： 29/72頁
文件大?。?/td> 302K
代理商： MPD705101GM-100-8ED
μ
PD705101
29
Table 13-2. Operating Status in HALT/STOP Mode
Function
Operating Status
Note 1
STOP Mode
Oscillation circuit
Operates
PLL synthesizer
Operates
Stops
Bus clock
Operates
Stops
CPU
Stops
Port output
Retained
Peripheral function
Operates
Stops
Internal data
Internal data such as registers of CPU retain status before HALT mode is set.
-
A1-A23
Undefined
High impedance when
HLDAK = 0
Undefined
D0-D31
High impedance
BCYST
1
High impedance when
HLDAK = 0
1
CS1-CS7
IORD, IOWR
MRD, WE, OE, LLMWR, LUMWR,
ULMWR, UUMWR
REFRQ, LLCAS, LUCAS, ULCAS,
UUCAS
1
Note 2
CBR self refresh
Note 4
RAS
Note 3
HLDRQ
Operates
Not accept
CLKOUT
Clock output (when clock output is not
disabled)
0
Notes 1.
Each pin is in the operating status during DMA transfer.
2.
Other than CBR refresh
3.
The previous status is retained before CBR refresh is executed. This pin is set to “1” after CBR refresh.
4.
CBR self refresh is not executed when it is disabled. In this case, the status of this pin before the STOP
mode is set is retained.
-
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