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參數(shù)資料
| 型號： | MPC9990FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 203K |
| 代理商： | MPC9990FAR2 |
MPC9990
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
294
Power Supply Filtering
The MPC9990 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply. Random noise on the
VCCA power supply impacts the device AC characteristics, for
instance I/O jitter. The MPC9990 provides separate power
supplies for the output buffers (VCCO) and the phase-locked
loop (VCCA) of the device.
Figure 9. Recommended Power Supply Filter
RF ≤ 9 W for VCC = 3.3V
2
7
Place VCCA filter and VCCO, VCC bypass ca
pacitors as close as possible to the device
VCCA
VCC
VCCO
RF
CF
6.8 F10 nF
33 ... 100 nF
3.3V±5%
+0.3 V
-0.1 V
1.8V
MPC9990
The purpose of this design technique is to isolate the high
switching noise digital outputs from the relatively sensitive in-
ternal analog phase-locked loop. In a digital system environ-
ment where it is difficult to minimize noise on the power sup-
plies a second level of isolation may be required. A simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC9990. Figure 9 illustrates a recommended pow-
er supply low-pass frequency filter scheme. The MPC9990
VCO frequency and phase stability is most susceptible to
noise with spectral content in the 300 kHz to 3 MHz range.
Therefore the filter should be designed to target this range.
The key parameter that needs to be met in the final filter design
is the DC voltage drop across the series filter resistor RF. The
maximum voltage drop on VCCA that can be tolerated is 135
mV with respect to VCC = 3.3V ± 5%, resulting in a lowest
allowable supply voltage for VCCA equal to 2.835 V.
From the data sheet the ICCA current (the current sourced
through the VCCA pin) is typically 11 mA (15 mA maximum),
assuming that the minimum of 3.0V (VCC=3.3V-5%-0.135V)
must be maintained on the VCCA pin. The resistor RF shown in
Figure 9 “Recommended Power Supply Filter” should have a
maximum resistance of 9
W to meet the voltage drop criteria.
The minimum resistance for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater 40 dB for noise whose
spectral content is above 300 kHz. In the example RC filter
shown in Figure 9 “Recommended Power Supply Filter”, the
filter cut-off frequency is 16.3 kHz and the noise attenuation at
300 kHz is approximately 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown (6.8
F || 10 nF) ensures
that a low impedance path to ground exists for frequencies well
above the bandwidth of the PLL. Although the MPC9990 has
several design features to minimize the susceptibility to power
supply noise (isolated power and grounds, internal voltage
regulation and fully differential PLL) there still may be applica-
tions in which overall performance is being degraded due to
system power supply noise. The power supply filter schemes
discussed in this section should be adequate to eliminate pow-
er supply noise related problems in most designs.
Recommended Power-up Sequence
The MPC9990 does not require any special supply ramp
sequence in case the system prorides all supply voltages
(3.3V and 1.8V) at the same time. The reference clock signal
(CLK, CLK) can be applied any time during or after the power
up sequence if VIN is smaller or equal VCC during the voltage
transition. Following are guidelines for the MPC9990 power-up
sequence in case the 3.3V and 1.8V voltage supply cannot be
applied at the same time:
HSTL output supply voltage VCCO must be powered up to the
specified voltage range before or at the same time as VCC.
VCCA can be powered up before, at the same time or after
VCC and VCCO.
At the time the power supplies are powered up, the device
should be reset (MR=0).
Apply the clock input signals to the PLL (CLK, CLK) after all
power supplies are stable. Then, MR can be deasserted
(MR=1). This will release the internal PLL which will attempt
to lock.
The time from MR deassertion to PLL lock will be specified
by the PLL lock time tLock. After the PLL achieved lock, the
AC characteristics are valid.
Outputs can be enabled by OE any time. QFB is not affected
by OE and the PLL can achieve lock even if OE is tied high
(OE = 1, disable).
2
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