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參數(shù)資料
| 型號： | MPC9990FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 203K |
| 代理商： | MPC9990FAR2 |
MPC9990
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
293
APPLICATIONS INFORMATION
Using the MPC9990 in zero-delay applications
Nested clock trees are typical applications for the MPC9990
Designs using the MPC9990 as PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from static fanout buffers. The
external feedback option of the MPC9990 clock driver allows
for its use as a zero delay buffer. By using the differential QFB
output pair as a feedback to the PLL the propagation delay
through the device is virtually eliminated. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device. The maxi-
mum insertion delay of the device in zero-delay applications is
measured between the reference clock input (CLK) and any
output. This effective delay consists of the static phase offset
(SPO), I/O jitter (phase or long-term jitter), feedback path delay
and the output-to-output skew error relative to the feedback
output.
Calculation of part-to-part skew
The MPC9990 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9990 are connected together, the maximum overall timing
uncertainty from the common CLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT(PER) + tJIT()
CF
This maximum timing uncertainty consist of 4 components:
static phase offset (SPO), output skew, feedback board trace
delay and I/O phase and period jitter. The output skew (tSK(O))
specification of the MPC9990 is different for single or for dual
frequency bank configurations. :
Figure 7. MPC9990 max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
CLKCommon
FBDevice 1
Any QDevice 1
FBDevice2
Any QDevice 2
Complementary signals are not shown. Signal refer
ences level is the differential voltage crosspoint VX
Due to the statistical nature of I/O jitter a rms value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (
± 3s) and single frequency configura-
tion is assumed, resulting in a worst case timing uncertainty
from input to any output of -495 ps to +245 ps relative to CLK.
tSK(PP) =
[–200ps...–50ps] + [–100ps...100ps] +
[–75ps...75ps] + [(30ps
@ –3)...(30ps@ 3)]
+ tPD, LINE(FB)
tSK(PP) =
[–495ps...+245ps] + tPD, LINE(FB)
Due to the frequency dependence of the I/O jitter, Figure 8
“Max. I/O Jitter versus frequency” can be used for a more pre-
cise timing performance analysis. The number for the I/O jitter
at a specific frequency can be substituted for the more general
datasheet specification number:
Figure 8. Max. I/O Jitter versus frequency
2
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