參數(shù)資料
型號： MPC9990FAR2
廠商： MOTOROLA INC
元件分類： 時鐘及定時
英文描述： PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： PLASTIC, LQFP-48
文件頁數(shù)： 7/10頁
文件大?。?/td> 203K
代理商： MPC9990FAR2
MPC9990
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
292
Table 7: AC CHARACTERISTICS (VCCI = VCCA = 3.3 V ±5%, VCCO = 1.7 to 2.1 V, TA = 0° to 70°C)a
Symbol
Characteristics
0
°C
25
°C
70
°C
Unit
Condition
y
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fIN
Input frequencyb for VCO_SEL
= 0 (high range)
1:1 ratio, ASEL=00
1:2 ratio, ASEL=01
3:4 ratio, ASEL=10
4:5 ratio, ASEL=11
Input frequencyb for VCO_SEL
= 1 (low range)
1:1 ratio, ASEL=00
1:2 ratio, ASEL=01
3:4 ratio, ASEL=10
4:5 ratio, ASEL=11
150.0
200.0
150.0
75.0
100.0
75.0
287.5
143.75
191.67
143.75
150.0
200.0
150.0
75.0
100.0
75.0
287.5
150.0
191.6
150.0
200.0
150.0
75.0
100.0
75.0
287.5
150.0
191.6
150.0
MHz
600 <
fVCO <
1150
MHz
300 <
fVCO <
575 MHz
fVCO
VCO frequency
VCO_SEL = 0 (high range)
VCO_SEL = 1 (low range)
600
300
1150
575
600
300
1150
575
600
300
1150
575
MHz
fOUT
Output frequencyc
287.5
MHz
SPO
Static phase offset, tPD
between CLK and FB
VCO_SEL=0
VCO_SEL=1
-200
-250
-50
-200
-250
-50
-200
-250
-50
ps
DC
Output duty cycle
45
50
55
45
50
55
45
50
55
%
tSK
Differential output skew
tSK(OB) within bankd
tSK(O) single frequencye
tSK(O) multiple frequencyf
tSK(OFB) QFB to QA0-6
for ASEL=00
for ASEL=01
for ASEL=10
for ASEL=11
tSK(O) QFB to QSYNC
85
25
135
65
–500
80
100
250
-115
-175
-115
-135
500
85
25
135
65
–500
80
100
250
-115
-175
-115
-135
500
85
25
135
65
–500
80
100
250
-115
-175
-115
-135
500
ps
Diff.
HSTL
outputs
VPPg
Minimum input swing
0.5
1
0.5
1
0.5
1
V
LVPECL
VCMR
Common mode range
1
VCC-0.
4
1
VCC-0
.4
1
VCC-0
.4
V
LVPECL
VDIF,OUT
Minimum output swing
0.6
0.8
0.6
0.8
0.6
0.8
V
HSTL
VX
Differential output crosspoint
voltage
0.64
0.9
0.68
0.9
0.68
1.0
V
HSTL
tJIT(CC)
Cycle-to-cycle jitter
fVCO >= 750 MHz
fVCO < 750 MHz
75
125
75
125
75
125
ps
tJIT(PER)
Period Jitter
VCO_SEL=0
VCO_SEL=1
75
125
75
125
75
125
ps
tJIT(IO)
I/O Phase Jitter RMS (1
σ)
600 MHz< fVCO <750 MHz
750 MHz< fVCO <900 MHz
900 MHz< fVCO <1150 MHz
50
40
30
50
40
30
50
40
30
ps
BW
PLL bandwidth
1:1 ratio, ASEL=00
1:2 ratio, ASEL=01
3:4 ratio, ASEL=10
4:5 ratio, ASEL=11
0.6-1.0
1.0-1.2
0.6-1.0
1.0-1.2
0.6-1.0
1.0-1.2
0.6-1.0
MHz
tr, tf
Output transition rate
0.8
2
0.8
2
0.8
2
V/ns
tLock
PLL lock time
10
ms
a. Refer to “HSTL Output Termination and AC Test Reference” for AC test conditions in Figure 6
b. The input frequency for the output configurations are limited by the VCO frequency range and the feedback divider.
c. fOUT at which output-to-output skew, VX and DC specification are still meet. fOUT is primary a function of fIN and the input-to-output fre-
quency ratio (M:N).
d. Output skew within bank A outputs (QA0-QA6) and output skew within bank B outputs (QB0-QB2).
e. Output skew within all outputs (QA0-QA6, QB0-QB2) running at the same output frequency.
f.
Output skew within all outputs (QA0-QA6, QB0-QB2) running at any output frequency.
g. VPP specifies the minimum input differential voltage required for switching.
2
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