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參數(shù)資料
| 型號(hào)： | MPC9990FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 203K |
| 代理商： | MPC9990FAR2 |
MPC9990
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
296
Figure 10. Output–to–output Skew tSK(O), tSK(OB)
Figure 11. Propagation delay (t, static phase
offset, SPO) test reference
Figure 12. Output Duty Cycle (DC)
Figure 13. I/O Jitter
The pin-to-pin skew is defined as the worst case difference in
propagation delay between any two similar delay path within a
single device (tSK(O)) or within a single output bank (tSK(OB))
The time from the PLL controlled edge to the non controlled edge,
divided by the time between PLL controlled edges, expressed as a
percentage
VX
tSK(O), tSK(OB)
QX
VX
QX
tP
T0
DC = tP/T0 x 100%
t()
TJIT) = |T0-T1mean|
CLK
FB
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles, measured at the FB signal (only true signal
shown)
QX
QY
VX
CLK
FB
VX
CLK
Figure 14. Cycle–to–cycle Jitter
Figure 15. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs, measured at an output (only true
signal shown)
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles (only true signal shown)
TN
TJIT(CC) = |TN-TN+1|
TN+1
TJIT(PER) = |TN-1/f0|
T0
tF
tR
VOH
Figure 16. Output Transition Time Test Reference
80%
20%
VOL
2
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