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參數(shù)資料
| 型號： | MPC972 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage PLL Clock Driver(低壓PLL時鐘驅(qū)動器) |
| 中文描述： | 低電壓PLL時鐘驅(qū)動器（低壓鎖相環(huán)時鐘驅(qū)動器） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 171K |
| 代理商： | MPC972 |
MPC972
TIMING SOLUTIONS
BR1333 — Rev 6
7
MOTOROLA
MPC972 is designed to specifically address this need. The
MPC972 monitors the relationship between the Qa and the
Qc banks of outputs. It provides a low going pulse, one period
in duration, one period prior to the coincident rising edges of
the Qa and Qc outputs. The duration and the placement of
the pulse is dependent on the higher of the Qa and Qc output
frequencies. The timing diagrams in the data sheet show the
various waveforms for the SYNC output. Note that the SYNC
output is defined for all possible combinations of the Qa and
Qc outputs even though under some relationships the lower
frequency clock could be used as a synchronizing signal.
Table 1. Programmable Output Frequency Relationships
(VCO_Sel=‘1’)
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1
fselc0
Qc
0
0
1
1
0
1
0
1
VCO/4
VCO/6
VCO/8
VCO/12
0
0
1
1
0
1
0
1
VCO/4
VCO/6
VCO/8
VCO/10
0
0
1
1
0
1
0
1
VCO/2
VCO/4
VCO/6
VCO/8
Table 2. Programmable Output Frequency Relationships
(VCO_Sel=‘1’)
fselFB2
fselFB1
fselFB0
QFB
0
0
0
0
0
0
1
1
0
1
0
1
VCO/4
VCO/6
VCO/8
VCO/10
1
1
1
1
0
0
1
1
0
1
0
1
VCO/8
VCO/12
VCO/16
VCO/20
Figure 4. Typical Skews Relative to QFB
–400
–300
–200
–100
0
100
200
300
400
Qc3
Qc2
Qc1
Qc0
Qb3
Qb2
Qb1
Qb0
Qa3
Qa2
Qa1
Qa0
p
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
30
40
50
60
70
80
90
100
110
I
Figure 5. Typical Phase Jitter versus Reference Frequency
I/O Jitter
Reference Clock Frequency (MHz)
VCO/4
VCO/6
VCO/8
1
σ
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