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參數(shù)資料
| 型號： | MPC972 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage PLL Clock Driver(低壓PLL時鐘驅動器) |
| 中文描述： | 低電壓PLL時鐘驅動器（低壓鎖相環(huán)時鐘驅動器） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | MPC972 |
MPC972
MOTOROLA
TIMING SOLUTIONS
2
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GNDO
VCO_Sel
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GNDO
Inv_Clk
G
Q
V
Q
G
Q
V
Q
E
G
Q
V
f
G
M
F
F
f
P
R
T
T
T
x
x
V
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MPC972
Figure 1. 52–Lead Pinout
(Top View)
All inputs have internal pull–up resistors (appr. 50K) except for the xtal1 and xtal2 pins.
FUNCTION TABLE 1
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1
fselc0
Qc
0
0
1
1
0
1
0
1
÷
4
÷
6
÷
8
÷
12
0
0
1
1
0
1
0
1
÷
4
÷
6
÷
8
÷
10
0
0
1
1
0
1
0
1
÷
2
÷
4
÷
6
÷
8
FUNCTION TABLE 2
*fselFB2
fselFB1
fselFB0
QFB
0
0
0
0
0
0
1
1
0
1
0
1
÷
4
÷
6
÷
8
÷
10
1
1
1
1
0
0
1
1
0
1
0
1
÷
8
÷
12
÷
16
÷
20
*If the fselFB2 is 1, it may be necessary to apply a reset after power
up to ensure synchronization between QFB and the other inputs.
FUNCTION TABLE 3
Control Pin
Logic ‘0’
Logic ‘1’
VCO_Sel
Ref_Sel
TCLK_Sel
PLL_En
MR/OE
Inv_Clk
VCO/2
TCLK
TCLK0
Bypass PLL
VCO
Xtal (PECL)
TCLK1
Enable PLL
Enable Outputs
Inverted Qc2, Qc3
Master Reset/Output Hi–Z
Non–Inverted Qc2, Qc3
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