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參數(shù)資料
| 型號： | MPC972 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Voltage PLL Clock Driver(低壓PLL時鐘驅(qū)動器) |
| 中文描述： | 低電壓PLL時鐘驅(qū)動器（低壓鎖相環(huán)時鐘驅(qū)動器） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | MPC972 |
MPC972
MOTOROLA
TIMING SOLUTIONS
6
AC CHARACTERISTICS
(TA = 0
°
to 70
°
C; VCC = 3.3V
±
5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
tpw
Output Rise/Fall Time
0.15
1.2
ns
0.8 to 2.0V, Note 6.
Output Duty Cycle
tCYCLE/2
–750
tCYCLE/2
±
500
tCYCLE/2
+750
ps
Note 6.
tpd
SYNC to Feedback
Propagation Delay
TCLK0
TCLK1
–270
–330
130
70
530
470
ps
Notes 6., 7.; QFB =
÷
8
tos
fVCO
fmax
Output-to-Output Skew
550
ps
Note 6.
VCO Lock Range
200
480
MHz
Maximum Output Frequency
Q (
÷
2)
Q (
÷
4)
Q (
÷
6)
Q (
÷
8)
125
120
80
60
MHz
Note 6.
tjitter
tPLZ, tPHZ
tPZL, tPZH
tlock
fMAX
6. 50
transmission line terminated into VCC/2.
7. tpd is specified for a 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input
reference periods. The tpd does not include jitter.
Cycle–to–Cycle Jitter (Peak–to–Peak)
±
100
ps
Note 6.
Output Disable Time
2
8
ns
Note 6.
Output ENable TIme
2
10
ns
Note 6.
Maximum PLL Lock Time
10
ms
Maximum Frz_Clk Frequency
20
MHz
APPLICATIONS INFORMATION
Programming the MPC972
The MPC972 is one of the most flexible frequency
programming devices in the Motorola timing solution
portfolio. With three independent banks of four outputs as
well as an independent PLL feedback output the total number
of possible configurations is too numerous to tabulate.
Table 1 tabulates the various selection possibilities for the
three banks of outputs. The divide numbers presented in the
table represent the divider applied to the output of the VCO
for that bank of outputs. To determine the relationship
between the three banks the three divide ratios would be
compared. For instance if a frequency relationship of 5:3:2
was desired the following selection could be made. The Qb
outputs could be set to
÷
10, the Qa outputs to
÷
6 and the Qc
outputs to
÷
4. With this output divide selection the desired
5:3:2 relationship would be generated. For situations where
the VCO will run at relatively low frequencies the PLL may not
be stable for the desired divide ratios. For these
circumstances the VCO_Sel pin allows for an extra
÷
2 to be
added into the clock path. When asserted this pin will
maintain the desired output relationships, but will provide an
enhanced lock range for the PLL. Once the output frequency
relationship is set and the VCO is in its stable range the
feedback output would be programmed to match the input
reference frequency.
The MPC972 offers only an external feedback to the PLL.
A separate feedback output is provided to optimize the
flexibility of the device. If in the example above the input
reference frequency was equal to the lowest output
frequency the feedback output would be set in the
÷
10 mode.
If the input needed to be half the lowest frequency output the
fselFB2 input could be asserted to halve the feedback
frequency. This action multiplies the output frequencies by
two relative to the input reference frequency. With 7 unique
feedback divide capabilities there is a tremendous amount of
flexibility. Again assume the above 5:3:2 relationship is
needed with the highest frequency output equal to 100MHz. If
one was also constrained because the only reference
frequency available was 50MHz the setup in Figure 6 could
be used. The MPC972 provides the 100, 66 and 40MHz
outputs all synthesized from the 50MHz source. With its
multitude of divide ratio capabilities the MPC972 can
generate almost any frequency from a standard, common
frequency already present in a design. Figure 7 and Figure 8
illustrate a few more examples of possible MPC972
configurations.
The MPC972 has one more programming feature added
to its arsenal. The Inv_Clk input pin when asserted will invert
the Qc2 and Qc3 outputs. This inversion will not affect the
output–output skew of the device. This inversion allows for
the development of 180
°
phase shifted clocks. This output
could also be used as a feedback output to the MPC972 or a
second PLL device to generate early or late clocks for a
specific design. Figure 9 illustrates the use of two MPC972’s
to generate two banks of clocks with one bank divided by 2
and delayed by 180
°
relative to the first.
SYNC Output Description
In situations where output frequency relationships are not
integer multiples of each other there is a need for a signal for
system synchronization purposes. The SYNC output of the
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