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參數(shù)資料
| 型號： | MPC93H51FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MPC93H51FA |
MPC93H51 is running at either 2x, 4x or 8x of the reference clock
frequency. The frequency of the QA, QB, QC and QD outputs is either the
one half, one fourth or one eighth of the selected VCO frequency and can be
configured for each output bank using the FSELA, FSELB, FSELC and
FSELD pins, respectively. The available output to input frequency ratios are
4:1, 2:1, 1:1, 1:2 and 1:4. The REF_SEL pin selects the differential
LVPECL (PECL_CLK and PECL_CLK) or the LVCMOS compatible
reference input (TCLK). The MPC93H51 also provides a static test mode
when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The test mode is intended for system
diagnostics, test and debug purpose. This test mode is fully static and the
minimum clock frequency specification does not apply. The outputs can be
disabled by deasserting the OE pin (logic high state). In PLL mode,
deasserting OE causes the PLL to loose lock due to no feedback signal
presence at EXT_FB. Asserting OE will enable the outputs and close the
phase locked loop, also enabling the PLL to recover to normal operation.
The MPC93H51 is fully 2.5V and 3.3V compatible and requires no external
loop filter components. All inputs except PECL_CLK and PECL_CLK
accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 W transmission lines. For
series terminated transmission lines, each of the MPC93H51 outputs can
drive one or two traces giving the devices an effective fanout of 1:18. The
device is packaged in a 7x7 mm2 32–lead LQFP package.
Output
Frequency
Range
(Min-Max)
(MHz)
Core
Voltage
(Spec)
(V)
I/O
Voltage
(Max)
(V)
Operating
Temperature
Range
(Min-Max)
(oC)
Input
Technology
Output
Technology
Number
of
Outputs
Package Description
240
3.3
0 to 70
LVCMOS,
LVPECL
LVCMOS
9
LQFP 32 7*7*1.4P0.8
MPC93H51 Parametrics
MPC93H51 Documentation
MPC93H51 Product Summary Page
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC93H51&nodeId=01HGpJ52483327 (2 of 3) [7/19/2004 9:49:11 AM]
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H52AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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