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參數(shù)資料
| 型號： | MPC93H51FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MPC93H51FA |
MPC93H51
MOTOROLA
Low Voltage PLL Clock Driver
7
Calculation of part-to-part skew
The MPC93H51 zero delay buffer supports applica-
tions where critical clock signal timing can be maintained
across several devices. If the reference clock inputs
(TCLK or PCLK) of two or more MPC93H51 are connect-
ed together, the maximum overall timing uncertainty from
the common TCLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 compo-
nents: static phase offset, output skew, feedback board
trace delay and I/O (phase) jitter:
Due to the statistical nature of I/O jitter a RMS value
(1
σ) is specified. I/O jitter numbers for other confidence
factors (CF) can be derived from Table 8.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation
a I/O jitter confidence factor of 99.7% (
± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to
any output of -251 ps to 351 ps relative to TCLK
(VCC=3.3V and fVCO = 400 MHz):
tSK(PP) = [–50ps...150ps] + [–150ps...150ps] +
[(17ps @ –3)...(17ps @ 3)] + tPD, LINE(FB)
tSK(PP) = [–251ps...351ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC=3.3V (17 ps
RMS). I/O jitter is frequency dependant with a maximum
at the lowest VCO frequency (200 MHz for the
MPC93H51). Applications using a higher VCO frequency
exhibit less I/O jitter than the AC characteristic limit. The
I/O jitter characteristics in Figure 4 can be used to derive
a smaller I/O jitter number at the specific VCO frequency,
resulting in tighter timing limits in zero-delay mode and
for part-to-part skew tSK(PP).
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
MPC93H51 zero-delay configuration
(feedback of QD4)
MPC93H51
TCLK
fref = 100 MHz
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
2 x 100 MHz
4 x 100 MHz
100 MHz (Feedback)
1
0
Figure 3. MPC93H51 maximum
device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
—t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Table 8. Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1σ
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
Figure 4. Maximum I/O Jitter (RMS)
versus frequency for VCC=3.3V
Max. I/O Jitter versus frequency
30
25
20
15
10
5
0
200
225
250
275
300
325
350
375
400
VCO frequency [MHz]
tJ
IT
(
)[p
s]
rms
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| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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