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參數(shù)資料
| 型號： | MPC93H51FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件頁數(shù)： | 15/15頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MPC93H51FA |
MPC93H51
MOTOROLA
Low Voltage PLL Clock Driver
9
two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain
the tight output-to-output skew of the MPC93H51. The
output waveform in Figure 7 “Single versus Dual Line
Termination Waveforms” shows a step in the waveform,
this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the
36
series resistor plus the output impedance does not
match the parallel combination of the line impedances.
The voltage wave launched down the two lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50W || 50
RS = 36W || 36
R0 = 14
VL = 3.0 ( 25 (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0ns).
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multi-
ple lines the situation in Figure 8 “Optimized Dual Line
Termination” should be used. In this case the series ter-
minating resistors are reduced such that when the paral-
lel combination is added to the output buffer impedance
the line impedance is perfectly matched.
Figure 9. TCLK MPC93H51 AC test reference for V
CC = 3.3V
Figure 10. PCLK MPC93H51 AC test reference
Figure 7. Single versus Dual Waveforms
VOLT
AGE
(V)
OutB
tD = 3.9386
OutA
tD = 3.8956
In
2
4
6
8
10
12
14
TIME (nS)
3.0
2.5
2.0
1.5
1.0
0.5
0
ZO = 50
Figure 8. Optimized Dual Line Termination
10
MPC93H51
OUTPUT
BUFFER
RS = 22
14
+ 22 || 22 = 50 || 50
25
= 25
Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC93H51 DUT
VTT
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
RT = 50
ZO = 50
MPC93H51 DUT
VTT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H52AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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