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參數(shù)資料
| 型號(hào)： | MPC93H51FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MPC93H51FA |
MPC93H51
6
Low Voltage PLL Clock Driver
MOTOROLA
APPLICATIONS INFORMATION
Programming the MPC93H51
The MPC93H51 clock driver outputs can be configured
into several divider modes, in addition the external feed-
back of the device allows for flexibility in establishing var-
ious input to output frequency relationships. The output
divider of the four output groups allows the user to con-
figure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency
ratios. The use of even dividers ensure that the output
duty cycle is always 50%. “Output Frequency Relation-
ship for an Example Configuration” illustrates the various
output configurations, the table describes the outputs us-
ing the input clock frequency CLK as a reference.
The output division settings establish the output rela-
tionship, in addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO
into a frequency range in which the PLL will be stable.
The design of the PLL supports output frequencies from
25 MHz to 240 MHz while the VCO frequency range is
specified from 200 MHz to 480 MHz and should not be
exceeded for stable operation.
Using the MPC93H51 in zero-delay applications
Nested clock trees are typical applications for the
MPC93H51. For these applications the MPC93H51 of-
fers a differential LVPECL clock input pair as a PLL refer-
ence. This allows for the use of differential LVPECL
primary clock distribution devices such as the Motorola
MC100EP111 or MC10EP222, taking advantage of its
superior low-skew performance. Clock trees using
LVPECL for clock distribution and the MPC93H51 as
LVCMOS PLL fanout buffer with zero insertion delay will
show significantly lower clock skew than clock distribu-
tions developed from CMOS fanout buffers.
Figure 1.
The external feedback option of the MPC93H51 PLL
allows for its use as a zero delay buffer. The PLL aligns
the feedback clock output edge with the clock input refer-
ence edge and virtually eliminates the propagation delay
through the device.
The remaining insertion delay (skew error) of the
MPC93H51 in zero-delay applications is measured be-
tween the reference clock input and any output. This ef-
fective delay consists of the static phase offset (SPO or
t()), I/O jitter (tJIT(), phase or long-term jitter), feedback
path delay and the output-to-output skew (tSK(O) relative
to the feedback output.
Figure 2.
Table 7. Output Frequency Relationshipa for an Example Configuration
a. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC
QD
0
2 * CLK
CLK
0
1
2 * CLK
CLK
÷ 2
0
1
0
4 * CLK
2 * CLK
CLK
2* CLK
0
1
4 * CLK
2 * CLK
CLK
0
1
0
2 * CLK
CLK
÷ 2
CLK
0
1
0
1
2 * CLK
CLK
÷ 2
CLK
÷ 2
0
1
0
4 * CLK
CLK
2 * CLK
0
1
4 * CLK
CLK
1
0
CLK
1
0
1
CLK
÷ 2
1
0
1
0
2 * CLK
CLK
2 * CLK
1
0
1
2 * CLK
CLK
1
0
CLK
÷ 2
CLK
1
0
1
CLK
÷ 2
CLK
÷ 2
1
0
2 * CLK
CLK
2 * CLK
1
2 * CLK
CLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H52AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93H52ACR2 | 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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