參數(shù)資料
型號： MPC93H51FA
廠商： MOTOROLA INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LQFP-32
文件頁數(shù)： 11/15頁
文件大?。?/td> 368K
代理商： MPC93H51FA
MPC93H51
MOTOROLA
Low Voltage PLL Clock Driver
5
Table 6. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = 0° to 70°C)a
a. AC characteristics apply for parallel output termination of 50
to V
TT
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequencyb
÷ 4 feedback
÷ 8 feedback
Static test mode
b.
The PLL will be unstable with a divide by 2 feedback ratio.
50
25
0
120
60
300
MHz
PLL_EN = 1
PLL_EN = 0
fVCO
VCO Frequency
200
480
MHz
fMAX
Maximum Output Frequencyb
÷ 2 output
÷ 4 output
÷ 8 output
100
50
25
240
120
60
MHz
frefDC
Reference Input Duty Cycle
25
75
%
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
VCMRc
c. V
CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the
input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Common Mode Range
PCLK, PCLK
1.2
VCC-0.9
V
LVPECL
tr, tfd
d. The MPC93H51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t
(
), can only be guaranteed if tr/tf are
within the specified range.
TCLK Input Rise/Fall Time
1.0
ns
0.8 to 2.0V
t()
Propagation Delay (static phase offset)
TCLK to EXT_FB
PCLK to EXT_FB
–150
0
+150
+250
ps
PLL locked
tsk(o)
Output-to-Output Skew
300
ps
DC
Output Duty Cycle
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
55
52.5
51.75
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ Output Disable Time
7.0
ns
tPZL, ZH Output Enable Time
6.0
ns
BW
PLL closed loop bandwidth
÷ 2 feedback
÷ 4 feedback
÷ 8 feedback
9.0 – 20.0
3.0 – 9.5
1.2 – 2.1
MHz
-3 db point of
PLL transfer
characteristic
tJIT(CC) Cycle-to-cycle jitter
÷ 4 feedback
Single Output Frequency Configuration
40
ps
RMS value
tJIT(PER) Period Jitter
÷ 4 feedback
Single Output Frequency Configuration
25
ps
RMS value
tJIT() I/O Phase Jitter
30
ps
RMS value
tLOCK Maximum PLL Lock Time
5
ms
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參數(shù)描述
MPC93H52AC 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, hig RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MPC93H52ACR2 功能描述:IC CLK GEN ZD 1:11 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
MPC93H52FA 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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