參數(shù)資料
型號(hào): MPC9330
廠商: Motorola, Inc.
英文描述: 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR
中文描述: 3.3 / 2.5V的1:6的LVCMOS PLL時(shí)鐘發(fā)生器
文件頁(yè)數(shù): 8/16頁(yè)
文件大?。?/td> 225K
代理商: MPC9330
MPC9330
MOTOROLA
TIMING SOLUTIONS
8
Table 10: MPC9330 Example Configurations (Internal Feedback: FB_SEL = 0)
frefa [MHz]
PWR_DN
FSELA
FSELB
0
0
0
FSELC
0
QA[0:1]:fref ratio
fref
4 (40-100 MHz)
fref
4 (40-100 MHz)
fref
4 (40-100 MHz)
fref
4 (40-100 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref (10-25 MHz)
QB[0:1]:fref ratio
fref
4 (40-100 MHz)
fref
4 (40-100 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
4 (40-100 MHz)
fref
4 (40-100 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref (10-25 MHz)
QC[0:1]:fref ratio
fref
2 (20-50 MHz)
fref
4
÷
3 (13.3-33.3 MHz)
fref
2 (20-50 MHz)
fref
4
÷
3 (13.3-33.3 MHz)
fref
2 (20-50 MHz)
fref
4
÷
3 (13.3-33.3 MHz)
fref
2 (20-50 MHz)
fref
4
÷
3 (13.3-33.3 MHz)
fref (10-25 MHz)
fref
2
÷
3 (6.67-16.67 MHz)
fref (10-25 MHz)
fref
2
÷
3 (6.67-16.67 MHz)
fref (10-25 MHz)
fref
2
÷
3 (6.67-16.67 MHz)
fref (10-25 MHz)
fref
2
÷
3 (6.67-16.67 MHz)
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
10.0-25.0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
fref (10-25 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref (10-25 MHz)
1
1
0
0
1
1
0
1
fref (10-25 MHz)
1
1
1
0
fref (10-25 MHz)
1
1
1
1
fref (10-25 MHz)
fref (10-25 MHz)
a.
fref is the input clock reference frequency (CCLK or XTAL)
Table 11: MPC9330 Example Configurations (External Feedback and PWR_DN = 0)
frefa
[MHz]
VCO
÷
4b
40-100
0
0
0
0
PLL
Feedback
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
0
fref (40-100 MHz)
fref (40-100 MHz)
fref
÷
2 (20-50 MHz)
fref
÷
3 (13.3-33.3MHz)
fref
÷
2 (20-50 MHz)
fref
÷
3 (13.3-33.3MHz)
fref (20-50 MHz)
fref
2
÷
3 (13.3-33.3 MHz)
fref (20-50 MHz)
fref
2
÷
3 (13.3-33.3 MHz)
fref (13.3-33.3 MHz)
1
fref (40-100 MHz)
fref (40-100 MHz)
fref
÷
2 (20-50 MHz)
fref
÷
2 (20-50 MHz)
fref
2 (40-100 MHz)
fref
2 (40-100 MHz)
fref (20-50 MHz)
0
1
0
fref (40-100 MHz)
0
1
1
fref (40-100 MHz)
VCO
÷
8c
20-50
1
0
0
fref (20-50 MHz)
1
0
1
fref (20-50 MHz)
1
1
0
fref (20-50 MHz)
1
1
1
fref (20-50 MHz)
fref
3 (40-100 MHz)
fref
3 (40-100 MHz)
fref
3
÷
2 (20-50 MHz)
fref
3
÷
2 (20-50 MHz)
fref (20-50 MHz)
fref
3 (40-100 MHz)
fref
3
÷
2 (20-50 MHz)
fref
3 (40-100 MHz)
fref
3
÷
2 (20-50 MHz)
VCO
÷
12d
13.3-33.3
0
0
1
0
1
1
fref (13.3-33.3 MHz)
1
0
1
fref (13.3-33.3 MHz)
1
1
1
fref (13.3-33.3 MHz)
a.
b.
c.
d.
fref is the input clock reference frequency (CCLK or XTAL)
QAx connected to FB_IN and FSELA=0, PWR_DN=0
QAx connected to FB_IN and FSELA=1, PWR_DN=0
QCx connected to FB_IN and FSELC=1, PWR_DN=0
Table 12: MPC9330 Example Configurations (External Feedback and PWR_DN = 1)
frefa
[MHz]
VCO
÷
16b
10-25
1
0
1
0
PLL
Feedback
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
0
fref (10-25 MHz)
fref
2 (20-50 MHz)
fref
2 (20-50 MHz)
fref (10-25 MHz)
fref (10-25 MHz)
fref
2
÷
3 (6.6-16.6 MHz)
fref (10-25 MHz)
fref
2
÷
3 (6.6-16.6 MHz)
fref (6.67-16.67 MHz)
1
fref (10-25 MHz)
1
1
0
fref (10-25 MHz)
1
1
1
fref (10-25 MHz)
fref
3 (20-50 MHz)
fref
3 (20-50 MHz)
fref
3
÷
2 (10-25 MHz)
fref
3
÷
2 (10-25 MHz)
fref (10-25 MHz)
fref
3 (20-50 MHz)
fref
3
÷
2 (10-25 MHz)
fref
3 (20-50 MHz)
fref
3
÷
2 (10-25 MHz)
VCO
÷
24c
6.67-16.67
0
0
1
0
1
1
fref (6.67-16.67 MHz)
1
0
1
fref (6.67-16.67 MHz)
1
1
1
fref (6.67-16.67 MHz)
a.
b.
c.
fref is the input clock reference frequency (CCLK or XTAL)
QAx connected to FB_IN and FSELA=1, PWR_DN=1
QCx connected to FB_IN and FSELC=1, PWR_DN=1
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