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參數(shù)資料
| 型號： | MPC9330 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 3.3 / 2.5V的1:6的LVCMOS PLL時鐘發(fā)生器 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 225K |
| 代理商： | MPC9330 |
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9330/D
Rev 1, 01/2002
1
Motorola, Inc. 2002
The MPC9330 is a 3.3V or 2.5V compatible, 1:6 PLL based clock
generator targeted for high performance low-skew clock distribution in
mid-range to high-performance telecomm, networking and computing
applications. With output frequencies up to 200 MHz and output skews
less than 150 ps1 the device meets the needs of the most demanding
clock applications. The MPC9330 is specified for the extended
temperature range of –40
°
C to +85
°
C.
Features
1:6 PLL based low-voltage clock generator
2.5V or 3.3V power supply
Generates clock signals up to 200 MHz
Maximum output skew of 150 ps1
On-chip crystal oscillator clock reference
Alternative LVCMOS PLL reference clock input
Internal and external PLL feedback
PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2,
x/3 or x/4
Supports zero-delay operation in external feedback mode
Synchronous output clock stop in logic low eliminates output runt pulses
Power_down feature reduces output clock frequency
Drives up to 12 clock lines
32 lead LQFP packaging
Ambient temperature range –40
°
C to +85
°
C
Pin and function compatible to the MPC930
Functional Description
The MPC9330 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9330 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback
input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback
path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback
configuration and with the available post-PLL dividers (divide-by-2, divide-by-4 and divide-by-6), the internal VCO of the
MPC9330 is running at either 4x, 8x, 12x, 16x or 24x of the reference clock frequency. In internal feedback configuration
(divide-by-16) the internal VCO is running 16x of the reference frequency. The frequency of the QA, QB, QC output banks is a
division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB and FSELC
pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible input as the reference clock signal. The
PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference
clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency
specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback
selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR
will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9330 output
clock stop control allows the outputs to start and stop synchronously in the logic low state, without the potential generation of runt
pulses.
The MPC9330 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except XTAL)
accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission lines. For series terminated transmission lines, each of the MPC9330 outputs can drive one or two traces giving the
devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package.
1. Design target, pending final characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
3.3V/2.5V 1:6 LVCMOS
PLL CLOCK GENERATOR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9330AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-6 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330ACR2 | 功能描述:IC PLL CLOCK GENERATOR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC9330FA | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330FAR2 | 制造商:Integrated Device Technology Inc 功能描述:MPC9330FAR2 - Tape and Reel |
| MPC9331 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3 V 1:6 LVCMOS PLL Clock Generator |
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