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參數(shù)資料
| 型號： | MPC9330 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 3.3 / 2.5V的1:6的LVCMOS PLL時鐘發(fā)生器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 225K |
| 代理商： | MPC9330 |
MPC9330
TIMING SOLUTIONS
5
MOTOROLA
Table 7: AC CHARACTERISTICS
(VCC = 3.3V
±
5%, TA = –40
°
C to 85
°
C)a b
Symbol
Characteristics
fref
PLL mode, external feedback
Min
50
25
16.67
12.5
8.33
12.5
Typ
Max
100
50
33.3
25
16.67
25
TBD
400
20
100
50
33.3
25
16.67
60
1.0
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
ns
ps
Condition
PLL locked
Input Reference Frequencyc
÷
4 feedbackd
÷
8 feedback
÷
12 feedback
÷
16 feedback
÷
24 feedback
÷
16 feedback)
PLL mode, internal feedback
Input Reference Frequency in PLL bypass modee
VCO Lock Frequency Rangef
Crystal Interface Frequency Rangeg
Output Frequency
fVCO
fXTAL
fMAX
200
10
50
25
16.67
12.5
8.33
40
÷
4 output
÷
8 output
÷
12 output
÷
16 output
÷
24 output
PLL locked
frefDC
tr, tf
t(
)
Reference Input Duty Cycle
CCLK Input Rise/Fall Time
Propagation Delay
(static phase offset)
Output-to-Output Skewh
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthj
PLL mode, external feedback
0.8 to 2.0V
FB_SEL=1 &
PLL locked
CCLK or PCLK to FB_IN
±
100
tsk(o)
DC
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(
)
BW
150
55
1.0
10
10
ps
%
ns
ns
ns
ps
ps
ps
kHz
kHz
kHz
kHz
kHz
ms
45
0.1
50
0.55 to 2.4V
RMS (1 )i
RMS (1 )
RMS (1 )
÷
4 feedback
÷
8 feedback
÷
12 feedback
÷
16 feedback
÷
24 feedback
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tLOCK
All AC characteristics are design targets and subject to change upon device characterization.
AC characteristics apply for parallel output termination of 50
to VTT.
PLL mode requires PLL_EN = 0 to enable the PLL.
÷
4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one
÷
2 output to FB_IN. See Table 1 to Table 3 for
other feedback configurations.
In bypass mode, the MPC9330 divides the input reference clock.
The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO
÷
FB.
The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
See application section for part–to–part skew calculation.
See application section for a jitter calculation for other confidence factors than 1 .
–3 dB point of PLL transfer characteristics.
Maximum PLL Lock Time
10
a.
b.
c.
d.
e.
f.
g.
h.
i.
j.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9330AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-6 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330ACR2 | 功能描述:IC PLL CLOCK GENERATOR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC9330FA | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330FAR2 | 制造商:Integrated Device Technology Inc 功能描述:MPC9330FAR2 - Tape and Reel |
| MPC9331 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3 V 1:6 LVCMOS PLL Clock Generator |
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