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參數(shù)資料
| 型號(hào)： | MPC9330 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 3.3 / 2.5V的1:6的LVCMOS PLL時(shí)鐘發(fā)生器 |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | MPC9330 |
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MPC9330
TIMING SOLUTIONS
3
MOTOROLA
Table 1: PIN CONFIGURATION
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
XTAL_IN, XTAL_OUT
Input
Analog
Crystal oscillator interface
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to an output
FB_SEL
Input
LVCMOS
Feedback select
REF_SEL
Input
LVCMOS
Reference clock select
PWR_DN
Input
LVCMOS
Output frequency and power down select
FSELA
Input
LVCMOS
Frequency divider select for bank A outputs
FSELB
Input
LVCMOS
Frequency divider select for bank B outputs
FSELC
Input
LVCMOS
Frequency divider select for bank C outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
CLK_STOP0-1
Input
LVCMOS
Clock output enable/disable
OE/MR
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
QA0-1, QB0-1, QC0-1
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). The MPC9330 requires an external RC
filter for the analog power supply pin VCC_PLL. Please see applications section for details.
Positive power supply for I/O and core. All VCC pins must be connected to the positive
power supply for correct operation
VCC
Supply
VCC
Table 2: FUNCTION TABLE
Control
Default
0
1
REF_SEL
0
The crystal oscillator output is the PLL reference clock
CCLK is the PLL reference clock
FB_SEL
0
Internal PLL feedback of 16. fVCO = 16 * fref
External feedback. Zero-delay operation
enabled for CCLK as reference clock
PLL_EN
1
Test mode with PLL disabled. The reference clock is
substituted for the internal VCO output. MPC9330 is fully
static and no minimum frequency limit applies. All PLL related
AC characteristics are not applicable.
Normal operation mode with PLL
enabled.
PWR_DN
1
VCO
÷
2 (High output frequency range)
Output divider
÷
2
Output divider
÷
2
Output divider
÷
4
VCO
÷
4 (Low output frequency range)
Output divider
÷
4
Output divider
÷
4
Output divider
÷
6
FSELA
0
FSELB
0
FSELC
0
CLK_STOP[0:1]
11
See Table 3
OE/MR
1
Outputs disabled (high-impedance state) and reset of the
device. During reset in external feedback configuration, the
PLL feedback loop is open. The VCO is tied to its lowest
frequency. The MPC9330 requires reset at power-up and after
any loss of PLL lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length of the reset
pulse should be greater than one reference clock cycle
(CCLK). Reset does not affect PLL lock in internal feedback
configuration.
Outputs enabled (active)
PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios.
See Table 1 to Table 3 for supported frequency ranges and output to input frequency ratios.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9330AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-6 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330ACR2 | 功能描述:IC PLL CLOCK GENERATOR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC9330FA | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330FAR2 | 制造商:Integrated Device Technology Inc 功能描述:MPC9330FAR2 - Tape and Reel |
| MPC9331 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3 V 1:6 LVCMOS PLL Clock Generator |
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