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| 型號： | MPC5606SEMLU |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BGA, LQFP-176 |
| 文件頁數(shù)： | 97/104頁 |
| 文件大小： | 1729K |
| 代理商： | MPC5606SEMLU |
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MPC560xS Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
92
3.19.8
I2C Timing
Table 49. I2C Input Timing Specifications — SCL and SDA
No. Symbol C
Parameter
Value
Unit
Min
Max
1
—
CC
D Start condition hold time
2
—
IP-Bus Cycle1
1 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
2
—
CC
D Clock low time
8
—
IP-Bus Cycle1
4
—
CC
D Data hold time
0.0
—
ns
6
—
CC
D Clock high time
4
—
IP-Bus Cycle1
7
—
CC
D Data setup time
0.0
—
ns
8
—
CC
D Start condition setup time (for repeated start condition only)
2
—
IP-Bus Cycle1
9
—
CC
D Stop condition setup time
2
—
IP-Bus Cycle1
Table 50. I2C Output Timing Specifications — SCL and SDA
No. Symbol C
Parameter
Value
Unit
Min
Max
11
1 Programming IBFD (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings
listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
The actual position is affected by the prescale and division values programmed in IFDR.
—
CC
D Start condition hold time
6
—
IP-Bus Cycle2
2 Inter Peripheral Clock is the clock at which the I2C peripheral is working in the device
—
CC
D Clock low time
10
—
IP-Bus Cycle1
33
3 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
—
CC
D SCL/SDA rise time
—
99.6
ns
—
CC
D Data hold time
7
—
IP-Bus Cycle1
—
CC
D SCL/SDA fall time
—
99.5
ns
—
CC
D Clock high time
10
—
IP-Bus Cycle1
—
CC
D Data setup time
2
—
IP-Bus Cycle1
—
CC
D Start condition setup time (for repeated start condition only)
20
—
IP-Bus Cycle1
—
CC
D Stop condition setup time
10
—
IP-Bus Cycle1
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