參數(shù)資料
型號: MPC5606SEMLU
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP176
封裝: 24 X 24 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BGA, LQFP-176
文件頁數(shù): 11/104頁
文件大?。?/td> 1729K
代理商: MPC5606SEMLU
MPC560xS Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Pinout and Signal Descriptions
Freescale Semiconductor
14
2.4
Signal Description
The following sections provide signal descriptions and related information about the functionality and configuration.
2.4.1
Pad Configuration during Reset Phases
All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are floating with the following exceptions:
RESET pad is driven low. This is released only after PHASE2 reset completion.
Main oscillator pads (EXTAL, XTAL) are tristate.
Pull-up:
— EVTI (208 MAPBGA package only)
— PB[5] (FAB)—Without external strong pull-down the device starts fetching from flash.
— PH[0] TCK
— PH[1] TDI
— PH[3] TMS
2.4.2
Voltage Supply Pins
Voltage supply pins are used to provide power to the device. Two dedicated pins are used for 1.2 V regulator stabilization.
Please note that there is a preferred power-up sequence for devices in the MPC560xS family. That sequence is described in the
following paragraphs.
Broadly, the supply voltages can be grouped as follows:
VREG HV supply (VDDR)
Generic IO supply or noise free supply
—VDDA
—VDDE_A
—VDDE_B
—VDDE_C
—VDDE_E
—VDDMA
—VDDMB
—VDDMC
—VDDPLL
LV supply (VDD12)
The preferred order of ramp up is as follows:
1. Generic IO supply or noise free supply
2. VREG HV supply (VDDR - Should be the last HV supply to ramp up. It is also OK if all HV supplies including VDDR
ramp up together)
3. LV supply
The reason for following this sequence is to ensure that when VREG releases its LVDs, the I/O and other HV segments are
powered properly. This is important because the MPC560xS does not monitor LVDs on I/O HV supplies.
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