參數(shù)資料
型號(hào)： MPC5606SEMLQR
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, LQFP-144
文件頁數(shù)： 87/104頁
文件大小： 1729K
代理商： MPC5606SEMLQR
Electrical Characteristics
MPC560xS Microcontroller Data Sheet, Rev. 2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
83
2. DCU_HSYNC causes the panel to start a new line. It always encompasses at least one PCLK pulse.
3. DCU_VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
4. DCU_DE acts like an output enable signal to the LCD panel. This output enables the data to be shifted onto the display.
When disabled, the data is invalid and the trace is off.
Figure 26. TFT LCD InterfaceTiming Overview1
3.19.3.1
Interface to TFT LCD Panels—Pixel Level Timings
Figure 27 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and data. All parameters
shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DCU_CLK signal
(meaning the data and sync signals change on the rising edge) and active-high polarity of the DCU_HSYNC, DCU_VSYNC
and DCU_DE signals. The user can select the polarity of the DCU_HSYNC and DCU_VSYNC signals via the SYN_POL
register, whether active-high or active-low. The default is active-high. The DCU_DE signal is always active-high.
Pixel clock inversion and a flexible programmable pixel clock delay are also supported. They are programmed via the DCU
Clock Confide Register (DCCR) in the system clock module.
The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H and FP_H
parameters are programmed via the HSYN PARA register. The PW_V, BP_V and FP_V parameters are programmed via the
VSYN_PARA register.
1. In Figure 26, the “DCU_LD[23:0]” signal is an aggregation of the DCU’s RGB signals—DCU_R[0:7], DCU_G[0:7] and
DCU_B[0:7].
Table 43. LCD Interface Timing Parameters—Horizontal and Vertical
No.
Symbol
C
Parameter
Value
Unit
1tPCP
CC
D Display pixel clock period
—
ns
2tPWH
CC
D HSYNC pulse width
PW_H
× t
PCP
ns
3tBPH
CC
D HSYNC back porch width
BP_H
× t
PCP
ns
4tFPH
CC
D HSYNC front porch width
FP_H
× t
PCP
ns
5tSW
CC
D Screen width
DELTA_X
× t
PCP
ns
6tHSP
CC
D HSYNC (line) period
(PW_H + BP_H + FP_H + DELTA_X )
× t
PCP
ns
7tPWV
CC
D VSYNC pulse width
PWV
× t
HSP
ns
LINE 1
LINE 2
LINE 3
LINE 4
LINE n-1
LINE n
DCU_VSYNC
DCU_HSYNC
DCU_DE
DCU_CLK
DCU_LD[23:0]
2
1
3
m-1
m
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